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in what case we consider the hold time violation

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kil

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hi alll,

while calculating the clock time period of deign we will cosnider the t setup time and time clock to output delay and combinatioanl delay but why we do not consider the hold time in calculating for time period of a circuit.

what does this hold time refers and what its signficance in design of sequential circits .

where exactly we cosnider the hold time violations.....................................


thanks,
kil
 

hi kil.
yes u are right hold time is not used in the calculation of Time period of the clock.
but Hold time signifies " how fast the launched data is reaching the capture f/f at the same edge of the launching clock" which directly affects the next state of the capture f/f.

pandit
 

Hi pandit_vlsi,

When hold fail, the chip does not work in any frequency (even 1hz).

Example.

Two flip-flops A and B. (Q of A) connect directly to (D of B). Assume the content of FF A is 1, FF of B is 0. Also assume the input of A (i.e. D) is 0.

When an active clock arrive, the correct value of A should be 0, and B should be 1.

Now, assume hold time is violated. The simplest this can happen is the clock of flip-flop A is faster then the clock of flip-flop B. In this case, the content of flip-flop A is update with the new value first (i.e content of flip-flop A changes from 1 to 0). Now, this new value of "0" is going to propagated to the input of flip-flop B. If this new value reach the D of flip-flop B before the clock reaches B, then there is a hold violation. In this case, the value of FF A is 0 (correct) and the value of FF B is 0 (wrong).

Regards,
Eng Han
www.eda-utilities.com
 

You can put a buffer between q of 1st flop and d of second flop. it will save time after that.
 

clock skew cause hold time violations to happen
 

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