In Post STA, Why need set_wire_load_model ?

[tuntable]

set_wire_load_model

Hi .

When I read 'ADVANCED ASIC CHIP SYNTHESIS' Book end part ,

I have some question.

In the post sta process , why need below option ?

set_wire_load_model ,
set_wire_load_mode .

We write actual RC delay value post sta script .
I think it is instead of set_wire_load_model , set_wire_load_mode .

I hope your thinking.

Thanks.

 

[philewar]

set_wire_load_mode

IMHO, if rc delay is not complete, wire load model is needed as a complementarity.

 

[farmerwang]

post sta

Assume only SDF file are back annotated in post-layout STA, wire load model still needed to caculate the wire capacitance for "max_transition" & "max_capacitance" check. So to avoid using the wire load model, net capacitance should be back annotated in the following format:
1. "set_load" file
2. DSPF/RSPF
3. SPEF