[SOLVED] Importing timing library into SOC encounter 10

[ebrahimi.khoy]

Hi,

I want to do some timing analysis using newer version of SOC encounter. In this regard, beside LEF file and verilog netlist, I should also provide the lib file for timing information. However in the newer version, in the import design diagram, this option is replaced with a pop-up menu which is empty. I think I should first introduce library and then use this diagram to import design.

If anyone has some experience with this newer version, I appreciate his/her help.

 

[rca]

Well you should used the script based instead the gui.
"
set init_verilog "design_top.v";
set init_top_cell "design_top";
set init_lef_file $list_of_lef_file;
set init_mmmc_file ./SCRIPTS/mmmc.tcl
set init_pwr_net "VDDD"
set init_gnd_net "VSSD"
init_design

the mmmc.tcl script contains the
create_rc_corner ...
create_library_set ...
create_delay_corner ...
create_constraint_mode ...
create_analysis_view ...
set_analysis_view ...