Locating several circuits on a FPGA chip often invites unexpected effects like the described one. Sensitive oscillators should always be moved as far as possible from "usual" logic circuits. Oscillators are affected by minor voltage variations while the logic circuits utilize comparator-like circuits (gates) which is only sensitive within the voltage window.
DC blocks on power lines help as we as using the gates around the oscillator area as an artificial "ground" may cure the problem. If not, simply take the oscillator "block" out of the FPGA and put it in a metal enclosure to prevent the unwanted effects. The higher the frequency, the more problems to expect.