Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Impact of surrounding logic - causes

Status
Not open for further replies.

HyperText

Junior Member level 2
Junior Member level 2
Joined
Nov 11, 2012
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,484
Hi,

https://i.imgur.com/vsNsjOh.png

suppose that I have an FPGA, and, based on the image above, that I have a circuit that is synthesized on the bottom-left part of the FPGA (green box). Furthermore, suppose that I synthesized another circuit (red box) that surrounds the first. This last circuit is a high power demanding circuit, and it is basically a "disturbing circuit" (it is useless). I'd like to know if the red "disturbing" circuit, which is located very closely to the green one, might influence in some way the green circuit (I'm talking about ANY influence it might have, such as timings constraints, power instability, or whatever, and why).

I'm asking this question because from experiments on Xilinx Spartan-3E FPGA I noticed that the green circuit behaves differently depending on the position of the red one. Assuming that I have a ring oscillator (green box) and that I can measure its frequency, I noticed that when the red disturbing circuit is close to the ring oscillator circuit, the ring oscillator's frequency is slower than when the red circuit is far away.
I'd like to investigate the causes of this behavior. Any direction is welcomed :)

Thanks
 

Locating several circuits on a FPGA chip often invites unexpected effects like the described one. Sensitive oscillators should always be moved as far as possible from "usual" logic circuits. Oscillators are affected by minor voltage variations while the logic circuits utilize comparator-like circuits (gates) which is only sensitive within the voltage window.
DC blocks on power lines help as we as using the gates around the oscillator area as an artificial "ground" may cure the problem. If not, simply take the oscillator "block" out of the FPGA and put it in a metal enclosure to prevent the unwanted effects. The higher the frequency, the more problems to expect.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top