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IMPACT : Can't open /dev/parport0: No such file or directory

promach

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I have the following IMPACT log with JTAG

UotiHA5.png


Code:
Can't open /dev/parport0: No such file or directory
Can't open /dev/parport1: No such file or directory
Can't open /dev/parport2: No such file or directory
Can't open /dev/parport3: No such file or directory

Code:
GUI --- Auto connect to cable...
// *** BATCH CMD : setCable -port auto
AutoDetecting cable. Please wait.
*** WARNING ***: When port is set to auto detect mode, cable speed is set to default 6 MHz regardless of explicit arguments supplied for setting the baud rates
PROGRESS_START - Starting Operation.
 Using windrvr6 driver.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusbdfwu.hex = 1030.
File version of /usr/share/xusbdfwu.hex = 1030.
 libusb-driver.so version: 2021-04-18 11:44:26.
Cable connection failed.
Connecting to cable (Parallel Port - parport0).
 libusb-driver.so version: 2021-04-18 11:44:26.
 LPT1 Base Address set from env variable = 0.
 LPT base address = 0000h.
 LPT1 Ecp Address set from env variable = 400.
 ECP base address = 0400h.
LPT port is already in use. rc = FFFFFFFFh
Cable connection failed.
Connecting to cable (Parallel Port - parport1).
 libusb-driver.so version: 2021-04-18 11:44:26.
 LPT2 Base Address set from env variable = 10.
 LPT base address = 0010h.
 LPT2 Ecp Address set from env variable = 410.
 ECP base address = 0410h.
LPT port is already in use. rc = FFFFFFFFh
Cable connection failed.
Connecting to cable (Parallel Port - parport2).
 libusb-driver.so version: 2021-04-18 11:44:26.
 LPT3 Base Address set from env variable = 20.
 LPT base address = 0020h.
 LPT3 Ecp Address set from env variable = 420.
 ECP base address = 0420h.
LPT port is already in use. rc = FFFFFFFFh
Cable connection failed.
Connecting to cable (Parallel Port - parport3).
 libusb-driver.so version: 2021-04-18 11:44:26.
 LPT4 Base Address set from env variable = 30.
 LPT base address = 0030h.
 LPT4 Ecp Address set from env variable = 430.
 ECP base address = 0430h.
LPT port is already in use. rc = FFFFFFFFh
Cable connection failed.
PROGRESS_END - End Operation.
Elapsed time =      2 sec.
Cable autodetection failed.
WARNING:iMPACT:923 - Can not find cable, check cable setup !
 

KlausST

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Hi,

We don't know what you expect.
We can not guess what programming hardware you use, at which port it is connected and if it is powered properly...

Klaus
 

promach

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I am using this FT2232H

Bus 001 Device 006: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
 

KlausST

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Hi,

FT2232H is a USB to UART bridge....
This does not match with the console text above, which only talks about parallel ports LPT...

Maybe it's time to give useful informations and ask a clear question.

Klaus
 

promach

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FT2232H does not just do USB-to-UART, it can also do USB-to-JTAG.

See https://ftdichip.com/wp-content/uploads/2020/07/AN_129_FTDI_Hi_Speed_USB_To_JTAG_Example.pdf

By the way, it is very very very confusing and frustrated to understand why would Xilinx ISE IMPACT tool require parallel ports LPT.
--- Updated ---

The JTAG cable detection issue is solved by inserting "source /opt/Xilinx/14.7/ISE_DS/settings64.sh" into $HOME/.bashrc

However, I still have the following CRC error even though IMPACT tool said that bitstream loading is completed.

WARNING:iMPACT:2217 - Error shows in the status register, CRC Error bit is NOT 0.

Code:
'1': Loading file '/home/phung/Downloads/DDR_backup/DDR_Xilinx_ISE/test_ddr3_memory_controller.bit' ...
done.
INFO:iMPACT:1777 - 
Reading /opt/Xilinx/14.7/ISE_DS/ISE/spartan6/data/xc6slx16.bsd...
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
UserID read from the bitstream file = 0xFFFFFFFF.
Data width read from the bitstream file = 1.
INFO:iMPACT:501 - '1': Added Device xc6slx16 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Active mode is BS
GUI --- Auto connect to cable...
INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.4
INFO:iMPACT - Digilent Plugin: found 1 device(s).
INFO:iMPACT - Digilent Plugin: opening device: "JtagSmt1", SN:210203367162
INFO:iMPACT - Digilent Plugin: User Name: JtagSmt1
INFO:iMPACT - Digilent Plugin: Product Name: Digilent JTAG-SMT1
INFO:iMPACT - Digilent Plugin: Serial Number: 210203367162
INFO:iMPACT - Digilent Plugin: Product ID: 30800151
INFO:iMPACT - Digilent Plugin: Firmware Version: 010A
INFO:iMPACT - Digilent Plugin: JTAG Port Number: 0
INFO:iMPACT - Digilent Plugin: JTAG Clock Frequency: 10000000 Hz
INFO:iMPACT - Current time: 4/18/21 8:53 PM
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': IDCODE is '01000100000000000010000010010011'
'1': IDCODE is '44002093' (in hex).
'1': : Manufacturer's ID = Xilinx xc6slx16, Version : 4
INFO:iMPACT - Current time: 4/18/21 8:53 PM
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Usercode is 'ffffffff'
INFO:iMPACT - Current time: 4/18/21 8:53 PM
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[2] RESERVED                                                               :         0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[8] RESERVED                                                               :         0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                  :         0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
'1': Reading status register contents...
[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         0
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         0
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         0
[9] MODE PIN M[0]                                                          :         0
[10] MODE PIN M[1]                                                         :         0
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         0
[13] DONE PIN                                                              :         0
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0
INFO:iMPACT - Current time: 4/18/21 8:53 PM
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': DNA = '000000000000000000000000000000000000000000000000000000000'
INFO:iMPACT - Current time: 4/18/21 8:53 PM
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Programming device...
 LCK_cycle = NoWait.
LCK cycle: NoWait
done.
'1': Reading status register contents...
[0] CRC ERROR                                                              :         1
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         0
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         0
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         1
[8] HSWAPEN PIN                                                            :         0
[9] MODE PIN M[0]                                                          :         0
[10] MODE PIN M[1]                                                         :         0
[11] RESERVED                                                              :         1
[12] INIT_B PIN                                                            :         0
[13] DONE PIN                                                              :         0
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0
WARNING:iMPACT:2217 - Error shows in the status register, CRC Error bit is NOT 0.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 1000 0001 0001 0000 
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT:188 - '1': Programming completed successfully.
 LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '1': Checking done pin....done.
'1': Programming terminated. DONE did not go high.
PROGRESS_END - End Operation.
Elapsed time =      0 sec.
 
Last edited:

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By the way, it is very very very confusing and frustrated to understand why would Xilinx ISE IMPACT tool require parallel ports LPT.
--- Updated ---

The JTAG cable detection issue is solved by inserting "source /opt/Xilinx/14.7/ISE_DS/settings64.sh" into $HOME/.bashrc

However, I still have the following CRC error even though IMPACT tool said that bitstream loading is completed.

WARNING:iMPACT:2217 - Error shows in the status register, CRC Error bit is NOT 0.
ISE is very old software and the original Xilinx programming cable used the parallel port on a PC. They updated ISE to use the newer JTAG programming cable, but I believe the software can still use the old parallel port cable.

Code:
INFO:iMPACT - '1': Checking done pin....done.
'1': Programming terminated. DONE did not go high.
PROGRESS_END - End Operation.
The bitstream file may have been (completely) sent, but the done bit never when high.
 

promach

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if the DONE bit never go HIGH after bitstream programming finished, then the programming process went terribly wrong.
This is also proven by visually inspecting the designated LED activity on the FPGA board.
 

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Well the CRC failing will also keep the done bit from going high, so yes the programming process failed.

You should make sure the device the programing file was made for is the correct device on the board being programmed.
 

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I have confirmed that I have the correct FPGA device name for JTAG programming

Could you tell more about why would CRC fails for the generated bitstream file ?
 

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The fpga keeps a running CRC of all the bits from the bitstream if they don't compute the same CRC in the bitstream itself then one or more bits that were receive are wrong.

Unless you are using a Xilinx supplied programming cable I would suspect the cable.

Check the signal integrity of the JTAG at the FPGA if you can.

If the above checks out then you'll have to start capturing the jtag sending of the bitstream to determine the error.
 

niciki

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It is not clear to me if you have 10 MHz or 6 MHz JTAG clock. Either way, reduce it to kHz rate and check again CRC status.

How long are cables from Xilinx programming cable to your board? A photo could be helpful.
 

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All of a sudden, the programming process succeeded. I had a feeling that this is some intermittent issue that will come back and haunt me in the future again.
Now, I got the bitstream loaded onto the FPGA, but how do I view the internal FPGA signals. I mean how to use ILA inside ISE ?

J0K5Btr.png
 

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Either by inserting it using the ISE GUI or generating the components and instantiating them in the code. Xilinx has documents that describe both methods.
 

niciki

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Learn about ChipScope Pro Analyzer, which is a debug for the ISE.
Main IPs are ICON, ILA, VIO, ATC2, and IBA.

For your case, to use ILA, you also need ICON.

IMHO ChipScope was way better (it gave possibility to make more complex signals relations/conditions) than what Logic Debug features in Vivado provide.
 

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ERROR:sim - Failed to generate file: chipscope_vio_xmdf_tcl
ERROR:sim - Error found during generation.

Why the generation error for chipscope ?

1619319751555.png
 

niciki

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As far as I know you should have a license to generate chipscope cores. Check it in a license manager - you should have a chipscope entry under your license version.

You use ISE 14.7 and Artix-7.
7 family was a transition from ISE to Vivado.
Click on Supported Families in this VIO core to make sure that your Artix is there. The error rised in getComponentName function.
 

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I am using Spartan-6 and it is supported by Chipscope-pro. My webpack license also shows that I have access to chipscope pro.
So, what is wrong ?

Family:spartan6
Device:xc6slx16
Package:ftg256
Speed Grade:-3

1619399332893.png
 

niciki

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Could you show your settings for this VIO core?

Is your main language Verilog perhaps? Unfortunately some cores only generate VHDL - don't know if this is relevant in this case.
 

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@niciki Changing the "Design Entry" setting also does not help to eliminate the error

Ypahf92.png
 

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The warnings you've been getting (e.g. post #17) show that the Behavioral simulation model is not supported.

I would switch it to None or Structural as tools (the scripts running them) are notorious for not handing misconfigurations (and errors) of their expected input all that well.

As a precaution I would shut off the ASY Symbol File generation. I would also check that the Flow Settings for Vendor = Other is correct. Use the Help button.
 

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