[IC design] design rule issue

[mm6349]

Hi all,

I have the question concerning the via or contact size in the layout design. Normally, the foundry will specify the exact size for both elements. What would happen if we design the via or contact larger than the specified "exact size" interm of the reliability of the fabricated chip; by ignoring both design rule issues?
I would try to fabrication my chip previously designed using 1.2 micron process and now we will use the 0.8um process without any design reduction.

 

[visualart]

It is difficultt hat you hold all datum.
Because the process is different, the parameter such as the width of the oxied layer ,is diiferent.

 

[ddtiantian]

There is a discussion of exact via size at