I need some help on Synopsys constraints.

[swgchlry]

When I synthesize a design, one port "reg[7:0] data" is an inout port, should I set the output delay or input delay or both? I only set the output delay on "data" in the top design,and then the SynDC indicated that some end-points in the sub design had not been set the max delay constraint. Does it aroused by the unenough constratins? If not, what's the problem?
thx

 

[jkfoo]

Since it is an inout port, you should include both input and output delays on the port.

 

[cnspy]

How do you implement the INOUT port? Not use PADS?

 

[ic_design]

As a digital pad, it had better be a input or output pin.

 

[haosg]

the better is set both input/output delay constraitn,
dc/ pt/ astro all can automatically handle it.
I don't know why, "some end point have no max delay constraitn" when you
have set ouptut delay,
if no added PAD, you should use "Z" to implement bidirectional

 

[tybhsl]

if i want to simulate a design containing a inout signal using active-hdl, what should I do?

 

[jinruan]

one port "reg[7:0] data" is an inout port
~~~~~~~~~~ is it right for define an inout port?