When I synthesize a design, one port "reg[7:0] data" is an inout port, should I set the output delay or input delay or both? I only set the output delay on "data" in the top design,and then the SynDC indicated that some end-points in the sub design had not been set the max delay constraint. Does it aroused by the unenough constratins? If not, what's the problem?
thx
the better is set both input/output delay constraitn,
dc/ pt/ astro all can automatically handle it.
I don't know why, "some end point have no max delay constraitn" when you
have set ouptut delay,
if no added PAD, you should use "Z" to implement bidirectional