program
Junior Member level 2
Hi every one
I wrote the VHDL code for the following equations so that we get a new value for b every clock cycle .
Please any body know how to rewrite this equation so that increase the speed of the design (frequency).
a : in std_logic_vector (11 downto 0);
b : out std_logic_vector (11 downto 0);
b(0) <= a(0) xor a(2) xor a(4) xor a(5) xor a(6) xor a(7) xor a(8) xor a(9) xor a(10) xor a(11) ;
b(1) <= a(2) xor a(4) ;
b(2) <= a(3) xor a(5) ;
b(3) <= a(4) xor a(6) ;
b(4) <= a(5) xor a(7) ;
b(5) <= a(6) xor a(8) ;
b(6) <= a(0) xor a(7) xor a(9) ;
b(7) <= a(1) xor a(8) xor a(10) ;
b(8) <= a(2) xor a(9) xor a(11) ;
b(9) <= a(0) xor a(1) xor a(3) xor a(4) xor a(5) xor a(6) xor a(7) xor a(8) xor a(9) xor a(11) ;
b(10) <= a(0) xor a(2) xor a(11) ;
b(11) <= a(0) xor a(3) xor a(4) xor a(5) xor a(6) xor a(7) xor a(8) xor a(9) xor a(10) xor a(11) ;
Thanks in advance
I wrote the VHDL code for the following equations so that we get a new value for b every clock cycle .
Please any body know how to rewrite this equation so that increase the speed of the design (frequency).
a : in std_logic_vector (11 downto 0);
b : out std_logic_vector (11 downto 0);
b(0) <= a(0) xor a(2) xor a(4) xor a(5) xor a(6) xor a(7) xor a(8) xor a(9) xor a(10) xor a(11) ;
b(1) <= a(2) xor a(4) ;
b(2) <= a(3) xor a(5) ;
b(3) <= a(4) xor a(6) ;
b(4) <= a(5) xor a(7) ;
b(5) <= a(6) xor a(8) ;
b(6) <= a(0) xor a(7) xor a(9) ;
b(7) <= a(1) xor a(8) xor a(10) ;
b(8) <= a(2) xor a(9) xor a(11) ;
b(9) <= a(0) xor a(1) xor a(3) xor a(4) xor a(5) xor a(6) xor a(7) xor a(8) xor a(9) xor a(11) ;
b(10) <= a(0) xor a(2) xor a(11) ;
b(11) <= a(0) xor a(3) xor a(4) xor a(5) xor a(6) xor a(7) xor a(8) xor a(9) xor a(10) xor a(11) ;
Thanks in advance