I am new to verilog Hardware Description Language.
I would like to know about writing test bench.
I need to write the a self checking test bench that fully exercises the Verilog UART module uart.v
The uart.v can be found at the following link. https://www.asic-world.com/examples/verilog/uart.html
As I beginner I am just learning the verilog, so I have no idea how to proceed with this.
So please If any body is familiar with writing testbench code, please give me some suggestions.
It would be a great help if anyone, who has already written the code can email to me sample code.
hi,
if u r using some simple simulators...it will be good to display the messages.
you can instance the RTL in a module and apply the stimulus.
but if u rusing cadence or VCS then dump the waveforms. and check it.
Hi,
A "self checking" will mean you ddon't have to visually check outputs from log/dump file - it should do "SELF Check". In UART - what you send is what you receive at output, so data integrity check is fairly simple if you have the right abstraction level. You should add assertions to do the protocol checks.
kalpana.aravind said:
Hi everyone,
I am new to verilog Hardware Description Language.
I would like to know about writing test bench.
We cover this in our CFV course. A course is about to be scheduled next week, see: www.noveldv.com and contact me at cvc.training <> gmail.com if interested.
I need to write the a self checking test bench that fully exercises the Verilog UART module uart.v
The uart.v can be found at the following link.
h**p://www.asic-world.com/examples/verilog/uart.html
My Humble Suggestion - please don't ask for the code - then how will you learn? You get RTL code off web, TB via email, then where will you learn?
Sorry if that hurts, but I would rather guide you in the correct direction than trying to be nice in email but in reality spoil your future - by giving you source code.