I'v designed RGMII IP CORE
but I really dont know how to write dc constraits script of design compiler, because
RGMII use rising&falling edge of a clock.
Can you describe more on your design's clock waveform? I thought DC's create_clock is able to constraint your design. You can man create_clock to take a closer look.
1. Define input clock.
2. Set_input_delay with respect to rising edge of the clock.
3. Set_input_delay with respect to falling edge of the clock using “-clock_fall” switch.