Sep 28, 2004 #1 G gold_kiss Full Member level 4 Joined Sep 11, 2002 Messages 211 Helped 7 Reputation 14 Reaction score 4 Trophy points 1,298 Activity points 1,789 pulse detection Hi, How do I write a code in verilog for pulse detection. The pulse width is assumed to be for 1 clock and is positive pulse. Thanks, Gold_kiss
pulse detection Hi, How do I write a code in verilog for pulse detection. The pulse width is assumed to be for 1 clock and is positive pulse. Thanks, Gold_kiss
Sep 28, 2004 #2 M masai_mara Advanced Member level 4 Joined Aug 13, 2004 Messages 118 Helped 8 Reputation 14 Reaction score 2 Trophy points 1,298 Activity points 1,426 Re: pulse detection declare a variable pulse_d1 and assign to it the value of pulse inside the clocked always block then- always @(posedge clk) begin if(pulse_d1 = 0 && pulse = 1) //pulse edge detected begin -------- -------- end end hope this helps.
Re: pulse detection declare a variable pulse_d1 and assign to it the value of pulse inside the clocked always block then- always @(posedge clk) begin if(pulse_d1 = 0 && pulse = 1) //pulse edge detected begin -------- -------- end end hope this helps.
Sep 29, 2004 #3 L linuxluo Full Member level 6 Joined Jul 26, 2002 Messages 331 Helped 7 Reputation 14 Reaction score 3 Trophy points 1,298 Activity points 2,514 Re: pulse detection hi, if you want to do it, you have to have a clock which frequency is twice than your sampled clock. otherwise you can use latch to decide.
Re: pulse detection hi, if you want to do it, you have to have a clock which frequency is twice than your sampled clock. otherwise you can use latch to decide.
Oct 5, 2004 #4 M malfunction Newbie level 6 Joined Sep 30, 2004 Messages 13 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 110 pulse detection A latch is great. the signal will be asserted at least for half of the clock period.
Jun 18, 2005 #5 T tom123 Advanced Member level 4 Joined Apr 4, 2005 Messages 116 Helped 5 Reputation 10 Reaction score 2 Trophy points 1,298 Activity points 2,338 Re: pulse detection The following code can realize your intent: wire signal_in; wire signal_posedge_detected; reg signal d; always @(posedge clk or negedge rst_n) begin if (~rst_n) signal_d <= #1 1'b0; else signal_d <= #1 signal_in; end assign signal_posedge_detected = signal_in & (~signal_d); gold_kiss said: Hi, How do I write a code in verilog for pulse detection. The pulse width is assumed to be for 1 clock and is positive pulse. Thanks, Gold_kiss Click to expand...
Re: pulse detection The following code can realize your intent: wire signal_in; wire signal_posedge_detected; reg signal d; always @(posedge clk or negedge rst_n) begin if (~rst_n) signal_d <= #1 1'b0; else signal_d <= #1 signal_in; end assign signal_posedge_detected = signal_in & (~signal_d); gold_kiss said: Hi, How do I write a code in verilog for pulse detection. The pulse width is assumed to be for 1 clock and is positive pulse. Thanks, Gold_kiss Click to expand...