How to write a code in Verilog for pulse detection?

[gold_kiss]

pulse detection

Hi,

How do I write a code in verilog for pulse detection. The pulse width is assumed to be for 1 clock and is positive pulse.

Thanks,
Gold_kiss

 

[masai_mara]

Re: pulse detection

declare a variable pulse_d1 and assign to it the value of pulse inside the clocked always block then-
always @(posedge clk)
begin
if(pulse_d1 = 0 && pulse = 1) //pulse edge detected
begin
--------
--------
end
end

hope this helps.

 

[linuxluo]

Re: pulse detection

hi,
if you want to do it, you have to have a clock which frequency is twice than your sampled clock.
otherwise you can use latch to decide.

 

[malfunction]

pulse detection

A latch is great.
the signal will be asserted at least for half of the clock period.

 

[tom123]

Re: pulse detection

The following code can realize your intent:

wire signal_in;
wire signal_posedge_detected;
reg signal d;

always @(posedge clk or negedge rst_n)
begin
if (~rst_n)
signal_d <= #1 1'b0;
else
signal_d <= #1 signal_in;
end

assign signal_posedge_detected = signal_in & (~signal_d);

Hi,

How do I write a code in verilog for pulse detection. The pulse width is assumed to be for 1 clock and is positive pulse.

Thanks,
Gold_kiss