how to use pll imbedded in FPGA ? similar questions for ADC

[zhonghan]

can i just use verilog-hdl code to realize a pll or a ADC after FPGA synthesis ?

 

[Jack// ani]

Your question is not clear!!

What do you intend to do? What are you trying to implement here?

 

[zhonghan]

Re: how to use pll imbedded in FPGA ? similar questions for

Sorry, i try to make my question clearer. Firstly , i want to know is there a pll or a ADC imbedded in FPGA( I just kown the existence of plls). Secondly , i want to know how to use them ( because i don't need external monolithic PLL or ADC if they are integrated in FPGA), is verilog code sufficient to implement them. I want to use the PLL to multiple the frequency of the reference clock and then to drive a counter. The adc is adopted to sample an anolog output of DC/DC converter. Medium speed and adjustable dynamic range are two main specs.

 

[Jack// ani]

Thats what I was expecting, glad you stated it explicitly!

Assuming you'll be targeting Xilinx devices.

It has what you call Delay Locked Loop(DLL), instead of PLL. To utilize DLL in your design you have to generate and instantiate HDL module in you design. Xilinx core generator will take parameter like multiplication/division factor to generate desired HDL file.

As such there in no on chip ADC peripheral on a FPGA chip. However, development boards do have external ADC/DAC chip which you have to configure on your own via SPI protocol. Datasheet is best place to start to learn more about them.

 

[zhonghan]

Re: how to use pll imbedded in FPGA ? similar questions for

Thank you very much for your detailed reply. I will try to find some related references.

 

[vlado14142]

Re: how to use pll imbedded in FPGA ? similar questions for

In FACT, there is FPGA with embedded PLL and ADC. Look at Actel's web page. Fusion series is good one-chip solution in some cases.