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How to use LPMs in the following code?

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pranavam

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Plz help...

1) Can u tell how to use LPMs in the following code efficiently without loosing the logic..
The device i selected is Altera cyclone II 2c20 F484c7 fpga....
And am not using any embedded memory blocks in the FPGA ( M4K)... Thus after compilation LEs consumed exceeds the available no. of LEs.. ( Because memory requirement in the program consumes LES instead of M4k..)

2) One more thing... Am a newbie in HDL design.. I dont know the standard writing styles.. Plz tell me how to optimize this code without loosing the logic





module final_4(strobe,data_inp,HEX0,HEX1,HEX2,HEX3,clk);
//output [9:0] LEDR;
//reg [9:0] LEDR;
input [6:0] data_inp;
input strobe;
input clk;
output [0:6] HEX0;
reg [0:6] HEX0=7'b1111111;
output [0:6] HEX1;
reg [0:6] HEX1=7'b1111111;
output [0:6] HEX2;
output [0:6] HEX3;
assign HEX2=7'b1111111;
assign HEX3=7'b1111111;
reg [20:0] le2 ;
reg [34:0] le1;
reg [2:0] rr;
reg [34:0] reg_train [0:77];
reg [13:0] luptable [0:35];
reg [5:0] addr_lup;
reg [6:0] addr;
reg [34:0] a [0:2];
reg [34:0] b [0:2];
reg [34:0] c [0:2];
reg [34:0] d [0:2];
reg [34:0] e [0:2];
reg [34:0] f [0:2];
reg [34:0] g [0:2];
reg [34:0] h [0:2];
reg [34:0] i [0:2];
reg [34:0] j [0:2];
reg [34:0] k [0:2];
reg [34:0] l [0:2];
reg [34:0] m [0:2];
reg [34:0] n [0:2];
reg [34:0] o [0:2];
reg [34:0] p [0:2];
reg [34:0] q [0:2];
reg [34:0] r [0:2];
reg [34:0] s [0:2];
reg [34:0] t [0:2];
reg [34:0] u [0:2];
reg [34:0] v [0:2];
reg [34:0] w [0:2];
reg [34:0] x [0:2];
reg [34:0] y [0:2];
reg [34:0] z [0:2];
reg [1:0] aaa;
reg [1:0] bbb;
reg [1:0] ccc;
reg [1:0] ddd;
reg [1:0] eee;
reg [1:0] fff;
reg [1:0] ggg;
reg [1:0] hhh;
reg [1:0] iii;
reg [1:0] jjj;
reg [1:0] kkk;
reg [1:0] lll;
reg [1:0] mmm;
reg [1:0] nnn;
reg [1:0] ooo;
reg [1:0] ppp;
reg [1:0] qqq;
reg [1:0] rrr;
reg [1:0] sss;
reg [1:0] ttt;
reg [1:0] uuu;
reg [1:0] vvv;
reg [1:0] www;
reg [1:0] xxx;
reg [1:0] yyy;
reg [1:0] zzz;




/*reg [5:0]s1;
reg [5:0]s2;
reg [5:0]s3;
reg [5:0]s4;*/
reg [5:0] sum [0:25];
reg [5:0] suma[0:2];
reg [5:0] sumb[0:2];
reg [5:0] sumc[0:2];
reg [5:0] sumd[0:2];
reg [5:0] sume[0:2];
reg [5:0] sumf[0:2];
reg [5:0] sumg[0:2];
reg [5:0] sumh[0:2];
reg [5:0] sumi[0:2];
reg [5:0] sumj[0:2];
reg [5:0] sumk[0:2];
reg [5:0] suml[0:2];
reg [5:0] summ[0:2];
reg [5:0] sumn[0:2];
reg [5:0] sumo[0:2];
reg [5:0] sump[0:2];
reg [5:0] sumq[0:2];
reg [5:0] sumr[0:2];
reg [5:0] sums[0:2];
reg [5:0] sumt[0:2];
reg [5:0] sumu[0:2];
reg [5:0] sumv[0:2];
reg [5:0] sumw[0:2];
reg [5:0] sumx[0:2];
reg [5:0] sumy[0:2];
reg [5:0] sumz[0:2];
reg [13:0] su [0:25];
reg ss;

integer jj=0;
integer mm=0;
integer ll=0;

always @(posedge strobe)
begin

case (rr)
3'b000:
begin le1[6:0] = data_inp;
le2[6:0] = le1[6:0];
rr=rr+3'b001;

end
3'b001:
begin le1[13:7] = data_inp;
le2[13:7] = le1[13:7];
rr=rr+3'b001;
mm=mm+1;
if (mm < 36)
begin
rr=3'b000;
addr_lup=addr_lup+6'b000001;
luptable[addr_lup]={le1[6:0],le1[13:7]};

end
end
3'b010:
begin
rr=rr+3'b001;
le1[20:14] = data_inp;
le2[20:14] = le1[20:14];
if( le2[13:0]==14'b11111111111111)
begin
ll=1;
addr=addr+le2[20:14];
case(le2[20:14])
7'b0000000 : begin
aaa=aaa+2'b01;
addr=addr+aaa;
// LEDR[9]=1'b1;

end
7'b0000011 : begin
bbb=bbb+2'b01;
addr=addr+bbb;
// LEDR[8]=1'b1;
end
7'b0000110 : begin
ccc=ccc+2'b01;
addr=addr+ccc;
// LEDR[7]=1'b1;
end
7'b0001001 : begin
ddd=ddd+2'b01;
addr=addr+ddd;
// LEDR[6]=1'b1;
end
7'b0001100 : begin
eee=eee+2'b01;
addr=addr+eee;
// LEDR[5]=1'b1;
end
7'b0001111 : begin
fff=fff+2'b01;
addr=addr+fff;
// LEDR[4]=1'b1;
end
7'b0010010 : begin
ggg=ggg+2'b01;
addr=addr+ggg;
end
7'b0010101 : begin
hhh=hhh+2'b01;
addr=addr+hhh;
end
7'b0011000 : begin
iii=iii+2'b01;
addr=addr+iii;
end
7'b0011011 : begin
jjj=jjj+2'b01;
addr=addr+jjj;
end
7'b0011110 : begin
kkk=kkk+2'b01;
addr=addr+kkk;
end
7'b0100001 : begin
lll=lll+2'b01;
addr=addr+lll;
end
7'b0100100 : begin
mmm=mmm+2'b01;
addr=addr+mmm;
end
7'b0100111 : begin
nnn=nnn+2'b01;
addr=addr+nnn;
end
7'b0101010 : begin
ooo=ooo+2'b01;
addr=addr+ooo;
end
7'b0101101 : begin
ppp=ppp+2'b01;
addr=addr+ppp;
end
7'b0110000 : begin
qqq=qqq+2'b01;
addr=addr+qqq;
end
7'b0110011 : begin
rrr=rrr+2'b01;
addr=addr+rrr;
end
7'b0110110 : begin
sss=sss+2'b01;
addr=addr+sss;
end
7'b0111001 : begin
ttt=ttt+2'b01;
addr=addr+ttt;
end
7'b0111100 : begin
uuu=uuu+2'b01;
addr=addr+uuu;
end
7'b0111111 : begin
vvv=vvv+2'b01;
addr=addr+vvv;
end
7'b1000010 : begin
www=www+2'b01;
addr=addr+www;
end
7'b1000101 : begin
xxx=xxx+2'b01;
addr=addr+xxx;
end
7'b1001000 : begin
yyy=yyy+2'b01;
addr=addr+yyy;
end
7'b1001011 : begin
zzz=zzz+2'b01;
addr=addr+zzz;
end


endcase
rr=3'b000;
end

le2=21'b0;
end
3'b011:
begin le1[27:21] = data_inp;
rr=rr+3'b001; end
3'b100:
begin le1[34:28] = data_inp;
rr=rr+3'b001; end
default: begin
if(ll==1)
begin reg_train[addr]=le1;
ll=0;
end
rr=3'b000;
// LEDR<=reg_train[1] [34:26] ;
jj=jj+1;
if (jj>=27)
addr=0;
else
begin
reg_train[addr]=le1;
addr=addr+7'b0000011;
end
end

endcase

end
//assign LEDR= le1[9:0];
integer ii;
integer kk;
integer hh;
integer larg;
integer classify;
always @(posedge clk)
begin
sum[0]=6'b111111;
sum[1]=6'b111111;
sum[2]=6'b111111;
sum[3]=6'b111111;
sum[4]=6'b111111;
sum[5]=6'b111111;
sum[6]=6'b111111;
sum[7]=6'b111111;
sum[8]=6'b111111;
sum[9]=6'b111111;
sum[10]=6'b111111;
sum[11]=6'b111111;
sum[12]=6'b111111;
sum[13]=6'b111111;
sum[14]=6'b111111;
sum[15]=6'b111111;
sum[16]=6'b111111;
sum[17]=6'b111111;
sum[18]=6'b111111;
sum[19]=6'b111111;
sum[20]=6'b111111;
sum[21]=6'b111111;
sum[22]=6'b111111;
sum[23]=6'b111111;
sum[24]=6'b111111;
sum[25]=6'b111111;
for(ii=0;ii<=2;ii=ii+1)
begin
suma[ii]=6'b000000;
sumb[ii]=6'b000000;
sumc[ii]=6'b000000;
sumd[ii]=6'b000000;
sume[ii]=6'b000000;
sumf[ii]=6'b000000;
sumg[ii]=6'b000000;
sumh[ii]=6'b000000;
sumi[ii]=6'b000000;
sumj[ii]=6'b000000;
sumk[ii]=6'b000000;
suml[ii]=6'b000000;
summ[ii]=6'b000000;
sumn[ii]=6'b000000;
sumo[ii]=6'b000000;
sump[ii]=6'b000000;
sumq[ii]=6'b000000;
sumr[ii]=6'b000000;
sums[ii]=6'b000000;
sumt[ii]=6'b000000;
sumu[ii]=6'b000000;
sumv[ii]=6'b000000;
sumw[ii]=6'b000000;
sumx[ii]=6'b000000;
sumy[ii]=6'b000000;
sumz[ii]=6'b000000;
end


for (ii=0;ii<=2;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
a[ii]=le1^reg_train[ii];
else
a[ii]=35'b1111111111111111111111111111111111;
end
for (ii=3;ii<6;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
b[ii-3]=le1^reg_train[ii];
else
b[ii-3]=35'b1111111111111111111111111111111111;
end
for (ii=6;ii<9;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
c[ii-6]=le1^reg_train[ii];
else
c[ii-6]=35'b1111111111111111111111111111111111;
end
for (ii=9;ii<12;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
d[ii-9]=le1^reg_train[ii];
else
d[ii-9]=35'b1111111111111111111111111111111111;
end
for (ii=12;ii<15;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
e[ii-12]=le1^reg_train[ii];
else
e[ii-12]=35'b1111111111111111111111111111111111;
end
for (ii=15;ii<18;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
f[ii-15]=le1^reg_train[ii];
else
f[ii-15]=35'b1111111111111111111111111111111111;
end
for (ii=18;ii<21;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
g[ii-18]=le1^reg_train[ii];
else
g[ii-18]=35'b1111111111111111111111111111111111;
end
for (ii=21;ii<24;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
h[ii-21]=le1^reg_train[ii];
else
h[ii-21]=35'b1111111111111111111111111111111111;
end
for (ii=24;ii<27;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
i[ii-24]=le1^reg_train[ii];
else
i[ii-24]=35'b1111111111111111111111111111111111;
end
for (ii=27;ii<30;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
j[ii-27]=le1^reg_train[ii];
else
j[ii-27]=35'b1111111111111111111111111111111111;
end
for (ii=30;ii<33;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
k[ii-30]=le1^reg_train[ii];
else
k[ii-30]=35'b1111111111111111111111111111111111;
end
for (ii=33;ii<36;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
l[ii-33]=le1^reg_train[ii];
else
l[ii-33]=35'b1111111111111111111111111111111111;
end
for (ii=36;ii<39;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
m[ii-36]=le1^reg_train[ii];
else
m[ii-36]=35'b1111111111111111111111111111111111;
end
for (ii=39;ii<42;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
n[ii-39]=le1^reg_train[ii];
else
n[ii-39]=35'b1111111111111111111111111111111111;
end
for (ii=42;ii<45;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
o[ii-42]=le1^reg_train[ii];
else
o[ii-42]=35'b1111111111111111111111111111111111;
end
for (ii=45;ii<48;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
p[ii-45]=le1^reg_train[ii];
else
p[ii-45]=35'b1111111111111111111111111111111111;
end
for (ii=48;ii<51;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
q[ii-48]=le1^reg_train[ii];
else
q[ii-48]=35'b1111111111111111111111111111111111;
end
for (ii=51;ii<54;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
r[ii-51]=le1^reg_train[ii];
else
r[ii-51]=35'b1111111111111111111111111111111111;
end
for (ii=54;ii<57;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
s[ii-54]=le1^reg_train[ii];
else
s[ii-54]=35'b1111111111111111111111111111111111;
end
for (ii=57;ii<60;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
t[ii-57]=le1^reg_train[ii];
else
t[ii-57]=35'b1111111111111111111111111111111111;
end
for (ii=60;ii<63;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
u[ii-60]=le1^reg_train[ii];
else
u[ii-60]=35'b1111111111111111111111111111111111;
end
for (ii=63;ii<66;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
v[ii-63]=le1^reg_train[ii];
else
v[ii-63]=35'b1111111111111111111111111111111111;
end
for (ii=66;ii<69;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
w[ii-66]=le1^reg_train[ii];
else
w[ii-66]=35'b1111111111111111111111111111111111;
end
for (ii=69;ii<72;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
x[ii-69]=le1^reg_train[ii];
else
x[ii-69]=35'b1111111111111111111111111111111111;
end
for (ii=72;ii<75;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
y[ii-72]=le1^reg_train[ii];
else
y[ii-72]=35'b1111111111111111111111111111111111;
end
for (ii=75;ii<78;ii=ii+1)
begin
if(reg_train[ii]!=35'b0)
z[ii-75]=le1^reg_train[ii];
else
z[ii-75]=35'b1111111111111111111111111111111111;
end

for (hh=0;hh<=2;hh=hh+1)
begin
for (ii=0;ii<=34;ii=ii+1)

begin
suma[hh]=suma[hh]+a[hh] [ii];

sumb[hh]=sumb[hh]+b[hh] [ii];

sumc[hh]=sumc[hh]+c[hh] [ii];

sumd[hh]=sumd[hh]+d[hh] [ii];

sume[hh]=sume[hh]+e[hh] [ii];

sumf[hh]=sumf[hh]+f[hh] [ii];

sumg[hh]=sumg[hh]+g[hh] [ii];

sumh[hh]=sumh[hh]+h[hh] [ii];

sumi[hh]=sumi[hh]+i[hh] [ii];

sumj[hh]=sumj[hh]+j[hh] [ii];

sumk[hh]=sumk[hh]+k[hh] [ii];

suml[hh]=suml[hh]+l[hh] [ii];

summ[hh]=summ[hh]+m[hh] [ii];

sumn[hh]=sumn[hh]+n[hh] [ii];

sumo[hh]=sumo[hh]+o[hh] [ii];

sump[hh]=sump[hh]+p[hh] [ii];

sumq[hh]=sumq[hh]+q[hh] [ii];

sumr[hh]=sumr[hh]+r[hh] [ii];

sums[hh]=sums[hh]+s[hh] [ii];

sumt[hh]=sumt[hh]+t[hh] [ii];

sumu[hh]=sumu[hh]+u[hh] [ii];

sumv[hh]=sumv[hh]+v[hh] [ii];

sumw[hh]=sumw[hh]+w[hh] [ii];

sumx[hh]=sumx[hh]+x[hh] [ii];

sumy[hh]=sumy[hh]+y[hh] [ii];

sumz[hh]=sumz[hh]+z[hh] [ii];
end
end

for (kk=0;kk<=2;kk=kk+1)
begin
if(suma[kk] < sum[0])
sum[0]=suma[kk];

if(sumb[kk] < sum[1])
sum[1]=sumb[kk];

if(sumc[kk] < sum[2])
sum[2]=sumc[kk];

if(sumd[kk] < sum[3])
sum[3]=sumd[kk];

if(sume[kk] < sum[4])
sum[4]=sume[kk];

if(sumf[kk] < sum[5])
sum[5]=sumf[kk];

if(sumg[kk] < sum[6])
sum[6]=sumg[kk];

if(sumh[kk] < sum[7])
sum[7]=sumh[kk];

if(sumi[kk] < sum[8])
sum[8]=sumi[kk];

if(sumj[kk] < sum[9])
sum[9]=sumj[kk];

if(sumk[kk] < sum[10])
sum[10]=sumk[kk];

if(suml[kk] < sum[11])
sum[11]=suml[kk];

if(summ[kk] < sum[12])
sum[12]=summ[kk];

if(sumn[kk] < sum[13])
sum[13]=sumn[kk];

if(sumo[kk] < sum[14])
sum[14]=sumo[kk];

if(sump[kk] < sum[15])
sum[15]=sump[kk];

if(sumq[kk] < sum[16])
sum[16]=sumq[kk];

if(sumr[kk] < sum[17])
sum[17]=sumr[kk];

if(sums[kk] < sum[18])
sum[18]=sums[kk];

if(sumt[kk] < sum[19])
sum[19]=sumt[kk];

if(sumu[kk] < sum[20])
sum[20]=sumu[kk];

if(sumv[kk] < sum[21])
sum[21]=sumv[kk];

if(sumw[kk] < sum[22])
sum[22]=sumw[kk];

if(sumx[kk] < sum[23])
sum[23]=sumx[kk];

if(sumy[kk] < sum[24])
sum[24]=sumy[kk];

if(sumz[kk] < sum[25])
sum[25]=sumz[kk];

end
luptable[0]=14'b11111111111111;
su[0]=luptable[sum[0]];
su[1]=luptable[sum[1]];
su[2]=luptable[sum[2]];
su[3]=luptable[sum[3]];
su[4]=luptable[sum[4]];
su[5]=luptable[sum[5]];
su[6]=luptable[sum[6]];
su[7]=luptable[sum[7]];
su[8]=luptable[sum[8]];
su[9]=luptable[sum[9]];
su[10]=luptable[sum[10]];
su[11]=luptable[sum[11]];
su[12]=luptable[sum[12]];
su[13]=luptable[sum[13]];
su[14]=luptable[sum[14]];
su[15]=luptable[sum[15]];
su[16]=luptable[sum[16]];
su[17]=luptable[sum[17]];
su[18]=luptable[sum[18]];
su[19]=luptable[sum[19]];
su[20]=luptable[sum[20]];
su[21]=luptable[sum[21]];
su[22]=luptable[sum[22]];
su[23]=luptable[sum[23]];
su[24]=luptable[sum[24]];
su[25]=luptable[sum[25]];

larg=14'b00000000;
for (kk=0;kk<26;kk=kk+1)
if(su[kk] > larg)
begin
larg=su[kk];
classify=kk;
end

case(classify)
0: begin
HEX0=7'b1001111;
HEX1=7'b1111111;
end
1: begin
HEX0=7'b0010010;
HEX1=7'b1111111;
end
2: begin
HEX0=7'b0000110;
HEX1=7'b1111111;
end
3: begin
HEX0=7'b1101100;
HEX1=7'b1111111;
end
4: begin
HEX0=7'b0100100;
HEX1=7'b1111111;
end
5: begin
HEX0=7'b0100000;
HEX1=7'b1111111;
end
6: begin
HEX0=7'b0001111;
HEX1=7'b1111111;
end
7: begin
HEX0=7'b0000000;
HEX1=7'b1111111;
end
8: begin
HEX0=7'b0001100;
HEX1=7'b1111111;
end
9: begin
HEX0=7'b0000001;
HEX1=7'b1001111;
end
10: begin
HEX0=7'b1001111;
HEX1=7'b1001111;
end
11: begin
HEX0=7'b0010010;
HEX1=7'b1001111;
end
12: begin
HEX0=7'b0000110;
HEX1=7'b1001111;
end
13: begin
HEX0=7'b1101100;
HEX1=7'b1001111;
end
14: begin
HEX0=7'b0100100;
HEX1=7'b1001111;
end
15: begin
HEX0=7'b0100000;
HEX1=7'b1001111;
end
16: begin
HEX0=7'b0001111;
HEX1=7'b1001111;
end
17: begin
HEX0=7'b0000000;
HEX1=7'b1001111;
end
18: begin
HEX0=7'b0001100;
HEX1=7'b1001111;
end
19: begin
HEX0=7'b0000001;
HEX1=7'b0010010;
end
20: begin
HEX0=7'b1001111;
HEX1=7'b0010010;
end
21: begin
HEX0=7'b0010010;
HEX1=7'b0010010;
end
22: begin
HEX0=7'b0000110;
HEX1=7'b0010010;
end
23: begin
HEX0=7'b1101100;
HEX1=7'b0010010;
end
24: begin
HEX0=7'b0100100;
HEX1=7'b0010010;
end
25: begin
HEX0=7'b0100000;
HEX1=7'b0010010;
end


default:
begin
HEX0=7'b0000000;
HEX1=7'b0000000;
end
endcase




end

//assign LEDR[9:0]=luptable[1] [9:0] ;

//assign trainop1=reg_train[0];
//assign trainop2=reg_train[1];

endmodule
 

Re: Plz help me...

Hi,
Try this: Go to Assignments -> Settings -> Analysis and synthesis -> On the "Auto RAM Replacement" Option.
OR the best way is to use the megafunctions provided by Quartus, where in you can specify the size, width and type of memory block.
Go to Tools -> MegaWizard Plug-in Manager -> Select suitabe Memory block corresponding to ur design and generate this core defining the parameters. Instantiate this component in ur design whereever required.
Good Luck:)
 

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