Port Map
Advanced Member level 4
Hi,
any body knows how to use ram_style attribute for an entity? where I should place the syntax?
syntax is as below:
assume I have a code like below and I want My_Fifo_A to be instantiated with distributed RAMs and My_Fifo_B to be instantiated with block RAMs;
any body knows how to use ram_style attribute for an entity? where I should place the syntax?
syntax is as below:
attribute ram_style : string;
attribute ram_style of <entity_name>: entity is "distributed";
attribute ram_style of <entity_name>: entity is "distributed";
assume I have a code like below and I want My_Fifo_A to be instantiated with distributed RAMs and My_Fifo_B to be instantiated with block RAMs;
Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity Entity1 is
port (
CLK : in std_logic;
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0)
);
end entity;
architecture Behavioral of Entity1 is
signal sSigSLV1 :std_logic_vector(7 downto 0):=(others=>'0');
component My_Fifo is
generic (Size:integer);
port (
CLK : in std_logic;
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0)
);
end component;
begin
--I want to use a distributed RAM for this entity
My_Fifo_A: My_Fifo
generic map(Size=>10)
port map(
CLK =>CLK,
A =>A,
B =>sSigSLV1
);
--I want to use a block RAM for this entity
My_Fifo_B: My_Fifo
generic map(Size=>1000)
port map(
CLK =>CLK,
A =>sSigSLV1,
B =>B
);
end Behavioral;