tia_design
Advanced Member level 4
tri state condition
Hi,
In my design I have a CMOS Class AB op amp powered by 5V (Vdd1), its output could be pulled up to 5V (Vdd2) or pulled down to 0V through an external resistor (4.7K). The design requirment is that whenever supply voltage Vdd1 is less than 4V, the op amp's output should be tri-state, that is, op amp's output should be 5V when it is pulled up to 5V Vdd2 through a resistor, be 0V if it is pulled down to 0V. For pull-up case, it is easy, I can use pull-up voltage to bias those PMOS in op amp into a off-state. But for pull-down case and when Vdd1 is about less 1V, how to get op amp output stage tri-state?
The CMOS process I'm using is 0.6u technology. Thanks!
Hi,
In my design I have a CMOS Class AB op amp powered by 5V (Vdd1), its output could be pulled up to 5V (Vdd2) or pulled down to 0V through an external resistor (4.7K). The design requirment is that whenever supply voltage Vdd1 is less than 4V, the op amp's output should be tri-state, that is, op amp's output should be 5V when it is pulled up to 5V Vdd2 through a resistor, be 0V if it is pulled down to 0V. For pull-up case, it is easy, I can use pull-up voltage to bias those PMOS in op amp into a off-state. But for pull-down case and when Vdd1 is about less 1V, how to get op amp output stage tri-state?
The CMOS process I'm using is 0.6u technology. Thanks!