how to tri-state output when the power supply is low?

[tia_design]

tri state condition

Hi,

In my design I have a CMOS Class AB op amp powered by 5V (Vdd1), its output could be pulled up to 5V (Vdd2) or pulled down to 0V through an external resistor (4.7K). The design requirment is that whenever supply voltage Vdd1 is less than 4V, the op amp's output should be tri-state, that is, op amp's output should be 5V when it is pulled up to 5V Vdd2 through a resistor, be 0V if it is pulled down to 0V. For pull-up case, it is easy, I can use pull-up voltage to bias those PMOS in op amp into a off-state. But for pull-down case and when Vdd1 is about less 1V, how to get op amp output stage tri-state?

The CMOS process I'm using is 0.6u technology. Thanks!

 

[erikl]

tristate opamp

... But for pull-down case and when Vdd1 is about less 1V, how to get op amp output stage tri-state?

Just put high-ohmic resistors between gate & source of both your output transistors,
so that with low or no power supply they will be off.

 

[tia_design]

tri-state op amp

If gate and source are connected through a resistor, the current still can go through drain to bulk through a diode. and op amp's output is still not tri-state

 

[erikl]

tristate comparator

If gate and source are connected through a resistor, the current still can go through drain to bulk through a diode. and op amp's output is still not tri-state

Yes. But only if an external voltage provided to the output is at least one diode forward voltage drop higher than vdd (or lower than vss). This of course is also valid for vdd=vss=0 . This cannot be avoided with MOS transistors.

 

[DenisMark]

opamp vdd pulled down

The first of all you need some detection circuit which will detect vdd1<4V condition and force opamp output in Z state. There aren't any problems with output nmos.
About pmos there are several option possible:
1) Use diode in series with output pmos if you have enough room. It will work in forward region during normal operation and in reverse in Z state. Be care in classical CMOS process you can't use forward biasing w/o latch-up possibility.
2) Use other pmos in series. But exchange source and drain. So it's parasitic diode will be forward biased in normal condition. Use gate to eliminate parasitic diode action in normal condition (rule of thumb: drop on this pmos should be less 350mV).
This is feasible solution for CMOS. It's some kind of controling rectifier.
3) if your pmos has similar breakdowns for source and drain junction, you can switch bulk through pmos switches and connect it either source or drain in depence of operation mode.
All of this solution are frequently used in "high voltage tolerant" I/O buffers.
May be not all of this points are clear explained. So let me know if you will face with some doubts.

 

[tia_design]

opamp tri state output

The first of all you need some detection circuit which will detect vdd1<4V condition and force opamp output in Z state. There aren't any problems with output nmos.
About pmos there are several option possible:
1) Use diode in series with output pmos if you have enough room. It will work in forward region during normal operation and in reverse in Z state. Be care in classical CMOS process you can't use forward biasing w/o latch-up possibility.
2) Use other pmos in series. But exchange source and drain. So it's parasitic diode will be forward biased in normal condition. Use gate to eliminate parasitic diode action in normal condition (rule of thumb: drop on this pmos should be less 350mV).
This is feasible solution for CMOS. It's some kind of controling rectifier.
3) if your pmos has similar breakdowns for source and drain junction, you can switch bulk through pmos switches and connect it either source or drain in depence of operation mode.
All of this solution are frequently used in "high voltage tolerant" I/O buffers.
May be not all of this points are clear explained. So let me know if you will face with some doubts.

Thank you, DenisMark, for your great information.
Yes, My design has a detection circuit which generate indication signal, which is equal to Vdd1 whenever Vdd1 >4V, and 0V whenever Vdd1<4V. I have no probem with output NMOS.
I can not use the first method you gave, which uses a series diode, because my deisgn need rail to rail output.

For second method, I attached a brief Class AB Op Amp based on your suggestion, that is, M14 and M15 in series and M15's source and drain is swapped.The two diodes are parasitic ones related to M14 and M15 respectively. Normal opamp only have M14 here, for tri-state, your suggestion is to introduce M15, right? I still have some question about this method. When Vdd1 is from 0 to 2V, and output is pulled down, the gate of M14/M15 is not well defined, that means, M14 and M15 could not be totally turned off. Then there will be some current runs through M14 and M15. That means output is not 0V. So, how to bias the gate of M14 and M15 so that M14 and M15 are turned off totally? Thank you very much for your help. Also, how to make the drop on M15 less than 350mV. My design require rail-to-rail output. Thanks!

 

[diemilio]

how to tristate

Dear tia_design,

I think that in this kind of situation adding a little bit of Digital circuitry will help you a lot. My suggestion is to include both a comparator and some passgates so that if Vdd1 is equal (or smaller) than Vdd2 by 1 volt (you can adjust this condition by designing you comparator appropriately) your output transistors are in either "normal operation" or "tristate".

If Vdd1 is equal to Vdd2 (5 V) the comparator will output Vdd2 (a digital 1) so the passgates connected to the previous stages of your amplifier will be "ON" allowing normal operation (they will add some resistance which can affect your poles, but other than that your circuit won't be affected).
If Vdd1 is smaller Vdd2 by 1 volt (Vdd1=4V) the comparator's output will be GND (a digital 0) enabling the passgates that connect Vdd2 and GND to the output PMOS and NMOS respectively (turning them off hence setting the output to high impedance).

Hope this helps,

diemilio