How to transmit one bit in a serial register, only once in an applied input duration?

[efevi]

Hello,

I have been searching for days but i could not find a solution, so here is the problem:

I want to implement a design that, when i press and then depress a "key"(like keyboard key, lets say switch), the input must only shift one memory element. However shift registers shift bits with each pos/neg edge clock. Therefore if i use a clocked shift register, then between my pressing and depressing of a switch, there will be hundreds, thousands clock cycles. Therefore my input will be shifted all through the memory elements, however i want only one shift.

For a solution, i thought about connecting the clock of the shift registers to the output of a delay element(i simply used buffer and added delay for sim. purpose), which is inputted by the load input of the shift registers. This way, when i press and depress a switch, there will be a pulse in load, and a delayed version of that pulse in clock input, one pos transition, and therefore one bit transition.

This works okay in the simulation, but delays disrupt signal transitions, where circuit is actually much much bigger. Who knows what will happen in hardware?

I tried wait statement before i knew that wait is not synthesisable.(It was very conforting that wait was seeming to solve any problem).

So there must be a more solid solution to this problem, i belive, if anyone can give an idea?

Thanks.

 

[moottii]

Why don't you make your shift register sensitive on your rising/falling edge of input?

 

[efevi]

Why don't you make your shift register sensitive on your rising/falling edge of input?

Lets say i have 4 dflipflops/latches to from a serial register.

Now, if my each flipflop/latches is not inputted a clock signal, and each of them are sensitive on rising edge of the input:
Lets, say initially all states are 0; and i apply an input of 1

1 ==> 0000 :now on the rising edge of the input the next states will be:
1000 :however, it does not stop here, since my second flip flop now have an input which just rose to 1 level
1100 :this process will continue until all states become 1 level:
1111 :this process will be almost instantenaous when i press switch(1) and very much before i depress it(0)

So, i don't think making flip flops rising edge sensitive on input solves the problem.
Therefore, the whole register(all 4 flip flops) must be sensitive to the rising edge of the input and shift one time.
However for now, i can't figure it out, by starting the design from flip flops /latches

 

[moottii]

Look at the below code

signal s_reg, s_next: std_logic_vector(3 downto 0);

process(input)
begin
   if(input'event and input = '1')then
      s_reg <= s_next;
   end if;
end process;

s_next <= input & s_reg(3 downto 1);
output <= s_reg(0);

 

[TrickyDicky]

I wouldnt use any old input as a clock - you're libable to run into issues with timing and skew. It is best to use a single system clock and use a synchronised version of the input as a clock enable.

 

[efevi]

Thanks for your advises, i had exams and didn't have time to think about it upto today.

With the clockless version of the project(with delays), i made some behavioral simulations and everything works fine. However when i make post translate simulation, i have always no output[000..0], implying something is wrong. I know that delays(#1 etc.) are for simulation purposes and i had hoped that since there are some logic circuits where i assigned these delays, in hardware although delays are ignored, these logic circuits would give me enough delay for proper operation. Nothing worked fine in hardware also. And i don't know either how xilinx is dealing with delays in post-translate simulation(Maybe it is ignoring delays and not assigning delays for the logic hardware either, i dont know).

Now, i am trying to implement the same project with clocks in registers as Trickydicky adviced:

I wouldnt use any old input as a clock - you're libable to run into issues with timing and skew. It is best to use a single system clock and use a synchronised version of the input as a clock enable.

The problem is that even if i enable the system clock with the load enable input(Load enable is an input that gives 1 for the time between i press an input and depress it, and 0 o.w.), then (assuming that the clock frequency is high enough to place more than 1 clock cycles for the duration that load enable is 1), my input will shift through the register as many times as the number of the clock cycles that exists in the duration of inputting. Which is a serious problem, since i have to shift the data only one time through shift register for an applied input.

I thought that i can handle this problem by building a counter for the clock. Counter's reset will be in accordance with the enable load(counter will work only when i input). Then i thought that, i can declare another load input for the registers, which will be 1 for only one value of the clockcount as in the following code:

always@(*)
begin
if(clockcount!=4'b0001) begin loadreg=1'b0; end
else begin loadreg=1'b1; end
end

This seems to save the day, however it is not. Since clockcount is 4 bits(2^4 =16 count), assuming a clock of 1 Mhz. 16 clock count is 16 microsec.

Now, i press an input at t=0. clockcounter starts to count. Lets say in 2 microsec. information is shifted one time in registers. Since i am not superfast in switching, i assume that i assume that i will not be able to depress the switch before t=0.5 seconds. Lets see how many times the input is shifted in the registers for 0.5 seconds?... Counter restarts 0.5sec/16microsec=31250 times, and since there is only one shift in each full count of the counter;

I am shifting the input 31250 times, for only one input applied.

The only solution that i can think is i can make lets say a 100 bit clock counter, and hope that i will not switch too long.

I hope i could explain myself clearly. I must be missing an easy point. Since this must not be this much complex.

Thank you for comments and advices.