efevi
Newbie level 5
Hello,
I have been searching for days but i could not find a solution, so here is the problem:
I want to implement a design that, when i press and then depress a "key"(like keyboard key, lets say switch), the input must only shift one memory element. However shift registers shift bits with each pos/neg edge clock. Therefore if i use a clocked shift register, then between my pressing and depressing of a switch, there will be hundreds, thousands clock cycles. Therefore my input will be shifted all through the memory elements, however i want only one shift.
For a solution, i thought about connecting the clock of the shift registers to the output of a delay element(i simply used buffer and added delay for sim. purpose), which is inputted by the load input of the shift registers. This way, when i press and depress a switch, there will be a pulse in load, and a delayed version of that pulse in clock input, one pos transition, and therefore one bit transition.
This works okay in the simulation, but delays disrupt signal transitions, where circuit is actually much much bigger. Who knows what will happen in hardware?
I tried wait statement before i knew that wait is not synthesisable.(It was very conforting that wait was seeming to solve any problem).
So there must be a more solid solution to this problem, i belive, if anyone can give an idea?
Thanks.
I have been searching for days but i could not find a solution, so here is the problem:
I want to implement a design that, when i press and then depress a "key"(like keyboard key, lets say switch), the input must only shift one memory element. However shift registers shift bits with each pos/neg edge clock. Therefore if i use a clocked shift register, then between my pressing and depressing of a switch, there will be hundreds, thousands clock cycles. Therefore my input will be shifted all through the memory elements, however i want only one shift.
For a solution, i thought about connecting the clock of the shift registers to the output of a delay element(i simply used buffer and added delay for sim. purpose), which is inputted by the load input of the shift registers. This way, when i press and depress a switch, there will be a pulse in load, and a delayed version of that pulse in clock input, one pos transition, and therefore one bit transition.
This works okay in the simulation, but delays disrupt signal transitions, where circuit is actually much much bigger. Who knows what will happen in hardware?
I tried wait statement before i knew that wait is not synthesisable.(It was very conforting that wait was seeming to solve any problem).
So there must be a more solid solution to this problem, i belive, if anyone can give an idea?
Thanks.