Thanks for your advises, i had exams and didn't have time to think about it upto today.
With the clockless version of the project(with delays), i made some behavioral simulations and everything works fine. However when i make post translate simulation, i have always no output[000..0], implying something is wrong. I know that delays(#1 etc.) are for simulation purposes and i had hoped that since there are some logic circuits where i assigned these delays, in hardware although delays are ignored, these logic circuits would give me enough delay for proper operation. Nothing worked fine in hardware also. And i don't know either how xilinx is dealing with delays in post-translate simulation(Maybe it is ignoring delays and not assigning delays for the logic hardware either, i dont know).
Now, i am trying to implement the same project with clocks in registers as Trickydicky adviced:
I wouldnt use any old input as a clock - you're libable to run into issues with timing and skew. It is best to use a single system clock and use a synchronised version of the input as a clock enable.
The problem is that even if i enable the system clock with the load enable input(Load enable is an input that gives 1 for the time between i press an input and depress it, and 0 o.w.), then (assuming that the clock frequency is high enough to place more than 1 clock cycles for the duration that load enable is 1), my input will shift through the register as many times as the number of the clock cycles that exists in the duration of inputting. Which is a serious problem, since i have to shift the data only one time through shift register for an applied input.
I thought that i can handle this problem by building a counter for the clock. Counter's reset will be in accordance with the enable load(counter will work only when i input). Then i thought that, i can declare another load input for the registers, which will be 1 for only one value of the clockcount as in the following code:
Code:
always@(*)
begin
if(clockcount!=4'b0001) begin loadreg=1'b0; end
else begin loadreg=1'b1; end
end
This seems to save the day, however it is not. Since clockcount is 4 bits(2^4 =16 count), assuming a clock of 1 Mhz. 16 clock count is 16 microsec.
Now, i press an input at t=0. clockcounter starts to count. Lets say in 2 microsec. information is shifted one time in registers. Since i am not superfast in switching, i assume that i assume that i will not be able to depress the switch before t=0.5 seconds. Lets see how many times the input is shifted in the registers for 0.5 seconds?... Counter restarts 0.5sec/16microsec=31250 times, and since there is only one shift in each full count of the counter;
I am shifting the input 31250 times, for only one input applied.
The only solution that i can think is i can make lets say a 100 bit clock counter, and hope that i will not switch too long.
I hope i could explain myself clearly. I must be missing an easy point. Since this must not be this much complex.
Thank you for comments and advices.