[SOLVED] How to tell the differece between MII & RMII interface?

[anujaa]

Can any one tell me the differece between MII & RMII interface....
or what is MII & RMII ?
n how to use those interfaces for ethernet PHY inteface

thanks
Anuja

 

[bernie75]

ethernet mii

RMII means reduced MII interface.
The interface clock is 50Mhz instead of 25Mhz. Due to this higher clock speed you need instead of 4 data signals (tx+rx) only 2.
Some control signals are also merged together.

For single Ethernet PHY/MAc I would recommend to use MII. MII is more popular and it is cheaper.

Bernie

 

[dipti]

mii to rmii

i think RMII is much more efficient than MII as concerned with no.of pins used.

 

[mukesh1981]

mii vs rmii

MII comprised of 16 pins for data and control is defined. and frequency is 25 mhz . but RMII is 8 pin interface and a single reference clock with 50 mhz

 

[e_ravikumarshinde]

rmii mii

RMII interface reduces your pin count on price of refrance clock speed.
You can easily get Phy wich suport RMII mode

 

[hynix]

mii vs rmii speed

Does usage of MII or RMII affect speed of traffic like 1Gbps or 10/100 Mbps.
Is it according speed chosen MII or RMII to be used ....? :|

 

[FvM]

mii signals

You may want to consult the specification of particular PHYs. As an obvious fact, you can't operate Gbit ethernet without a GMII (Gigabit Media Independant Interface) respectivly RGMII. In other words, MII or RMII doesn't allow Gbit transmission.

 

[xvibe]

mii rmii

No, you don't loose nothing. You still have 100Mbps in the RMII (2 data lines x 50MHz = 100MBps) and the control signals are still there as in the MII.
For 1Gbps you need RGMII - 4 DDR data lines and 1 control line plus clock (125MHz). So 4x125=500Gbps but because the data lines are DDR signals you get 2x4x125=1Gbps.
Also, there the serial equivalent for the MII signals, It's the SMII, 1 data line and one 125Mhz clock. It's 125Mhz clock because 2 of the bits are used control. And for 1Gbps you have SGMII with 1 data line and one 1.25GHz clock.
Have a look at the IEEE 802.3 standard for better explanation.

 

[kpec1988]

Re: mii rmii

No, you don't loose nothing. You still have 100Mbps in the RMII (2 data lines x 50MHz = 100MBps) and the control signals are still there as in the MII.
For 1Gbps you need RGMII - 4 DDR data lines and 1 control line plus clock (125MHz). So 4x125=500Gbps but because the data lines are DDR signals you get 2x4x125=1Gbps.
Also, there the serial equivalent for the MII signals, It's the SMII, 1 data line and one 125Mhz clock. It's 125Mhz clock because 2 of the bits are used control. And for 1Gbps you have SGMII with 1 data line and one 1.25GHz clock.
Have a look at the IEEE 802.3 standard for better explanation.

hi

If you want to design compact board then RMII is better choise but your coast is increase in RMII because 50MHZ oscillator is coastly then 25MHZ oscillator and radiated emission problem is also there in RMII mode if you don`t care of layout.

---------- Post added at 22:32 ---------- Previous post was at 22:31 ----------

hi

If you want to design compact board then RMII is better choise but your coast is increase in RMII because 50MHZ oscillator is coastly then 25MHZ oscillator and radiated emission problem is also there in RMII mode if you don`t care of layout.

 

[philby1985]

Re: mii signals

You may want to consult the specification of particular PHYs. As an obvious fact, you can't operate Gbit ethernet without a GMII (Gigabit Media Independant Interface) respectivly RGMII. In other words, MII or RMII doesn't allow Gbit transmission.

Is RGMII backwards compatible with RMMI? So if (for example) you are only interested in using a Gbit phy chip in 100Mbit mode will the interface revert to RMII?

 

[padmaneela]

Re: mii signals

Can i use 10 Mbps or 100 Mbps Ethernet MAC controller with RMII/MIIM interface controller to get 1Gbps?? any Bridge or Transceiver available?