Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to synthesis top level?

Status
Not open for further replies.

quan228228

Full Member level 4
Joined
Mar 23, 2006
Messages
196
Helped
16
Reputation
32
Reaction score
3
Trophy points
1,298
Activity points
2,571
Hi,

I synthesis a design using bottum-up method. When i finish the core synthesis, how can i set the top constraint for top level?
In top level, it includes IO pads, core design, PHY, PLL etc. how can set set_driving_cell, set_load etc..?


Thanks!

David
 

rsrinivas

Advanced Member level 1
Joined
Oct 10, 2006
Messages
415
Helped
50
Reputation
100
Reaction score
12
Trophy points
1,298
Location
bengalooru
Activity points
3,704
Mostly u use bottom up approcah to charcterize ur sub modules constraints.
once u have got the constraints for all the submodules u compile all the files and elaborate with ur top level module name option.
like elaborate counter
where counter is ur top level module name wherein u have all the sub modules instantiated
a compile command witout any switch in DC is a top down compile.
to down compile is efficient than ur bottom up compile.
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
use bottom up approach to characterize ur sub modules constraints
How should I exactly do so? What commands should I use let's say in Synopsys Design Compiler?
Should I read already synthesized modules and characterize them in order to meet their internal timing?
Thank you!
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
Dם you t a 'dont_touch' attribute to the sub-modules, which you read inside of the top hierarchy?
On which stage do you apply the top-level constraints?
When do you need to use an 'characterize' command?
Thank you!
 

sam536

Full Member level 5
Joined
Jul 4, 2007
Messages
245
Helped
50
Reputation
102
Reaction score
34
Trophy points
1,308
Location
Tokyo
Activity points
3,028
Below are the steps for top level synthesis.
1. Read all the sub modules .
2. Link the design.
3. Put Dont touch on all the sub modules.
4. Apply the IO level constraints.
5. Apply the top level SDC, which need all the clock definitions, Exceptions and etc.
6. Apply the constraints for glue logic(if any).
7. Synthesize the design with compile or compile_ultra command.
8. Check the timing for top level as sub modules.

Regards , sam
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
Let's say we have a Top Level 'A' and two synthesized sub-modules 'B' and 'C' instantiated in this Top level.
1) When we read the netlists of 'B' and 'C' modules, should we put 'set_dont_touch' attribute on their netlists?
2) In order to synthesize interfaces between the 'A', 'B', and 'C' modules, should we just use 'elaborate' command or also 'compile'?
3) Will the synthesizer change the netlists of 'B' and 'C' modules if they met timing and other constraints on their module-level synthesis?
Thank you!
 

dftrtl

Banned
Joined
Feb 1, 2011
Messages
349
Helped
76
Reputation
152
Reaction score
73
Trophy points
1,308
Location
Bangalore
Activity points
0
If I understand your question, You need to write top level constraints for TOP level synthesis.
If you read .lib of SUB modules nothing will change at SUB modules level by TOP modules synthesis. Otherwise to meet timing it can change SUB Modules also.
 

englishdogg

Full Member level 5
Joined
Jan 10, 2012
Messages
250
Helped
38
Reputation
76
Reaction score
39
Trophy points
1,308
Location
India
Activity points
2,742
I agree with dftrtl.. Even i underdstand the question as how to write the top level constraints

@quan228228

This is interesting - may i ask how did you get the constraints at the submodule level; cause you would ahve had the need to add IO delays for these sub-modules as well.
I believe there are tools in the market which help you pull-up your block level constraints at the top level - though cant recall the name as for now. try google uncle :)

Also if you wish to perform cross boundary optimization then you do nopt need to preserve the sub-modules - if you do not wish then you can preserve / dont_touch or I like the idea of libs
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
1) If I use the libs instead of sub-modules for Top-Level optimization, then who the final netlist should be assembled? Will the sub-modules still stay libs in the final Netlist?
2) Why to create libs for sub-modules and not just to read their netlists? What are the pros and cons?
3) Should I provide special commands/attributes for the cross boundary synthesis optimization?
4) What's difference between applying and not applying a flatten command on the hierarchical design during the synthesis? Will the difference be just in a netlist structure or also in the optimization results?
Thank you!
 

englishdogg

Full Member level 5
Joined
Jan 10, 2012
Messages
250
Helped
38
Reputation
76
Reaction score
39
Trophy points
1,308
Location
India
Activity points
2,742
1. Yes
2. Cons - huge runtime, need to close / review timing again in this block, no need for formal verification again ; Pro - will be opposite of CON
3. If you using libs this is useless - since you cant go inside a hard logic and optimize
4. Difference will be in both cases Structure and optimization
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top