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how to synthesis top level?

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Full Member level 4
Mar 23, 2006
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I synthesis a design using bottum-up method. When i finish the core synthesis, how can i set the top constraint for top level?
In top level, it includes IO pads, core design, PHY, PLL etc. how can set set_driving_cell, set_load etc..?



Mostly u use bottom up approcah to charcterize ur sub modules constraints.
once u have got the constraints for all the submodules u compile all the files and elaborate with ur top level module name option.
like elaborate counter
where counter is ur top level module name wherein u have all the sub modules instantiated
a compile command witout any switch in DC is a top down compile.
to down compile is efficient than ur bottom up compile.

use bottom up approach to characterize ur sub modules constraints
How should I exactly do so? What commands should I use let's say in Synopsys Design Compiler?
Should I read already synthesized modules and characterize them in order to meet their internal timing?
Thank you!

Dם you t a 'dont_touch' attribute to the sub-modules, which you read inside of the top hierarchy?
On which stage do you apply the top-level constraints?
When do you need to use an 'characterize' command?
Thank you!

Below are the steps for top level synthesis.
1. Read all the sub modules .
2. Link the design.
3. Put Dont touch on all the sub modules.
4. Apply the IO level constraints.
5. Apply the top level SDC, which need all the clock definitions, Exceptions and etc.
6. Apply the constraints for glue logic(if any).
7. Synthesize the design with compile or compile_ultra command.
8. Check the timing for top level as sub modules.

Regards , sam

Let's say we have a Top Level 'A' and two synthesized sub-modules 'B' and 'C' instantiated in this Top level.
1) When we read the netlists of 'B' and 'C' modules, should we put 'set_dont_touch' attribute on their netlists?
2) In order to synthesize interfaces between the 'A', 'B', and 'C' modules, should we just use 'elaborate' command or also 'compile'?
3) Will the synthesizer change the netlists of 'B' and 'C' modules if they met timing and other constraints on their module-level synthesis?
Thank you!

If I understand your question, You need to write top level constraints for TOP level synthesis.
If you read .lib of SUB modules nothing will change at SUB modules level by TOP modules synthesis. Otherwise to meet timing it can change SUB Modules also.

I agree with dftrtl.. Even i underdstand the question as how to write the top level constraints


This is interesting - may i ask how did you get the constraints at the submodule level; cause you would ahve had the need to add IO delays for these sub-modules as well.
I believe there are tools in the market which help you pull-up your block level constraints at the top level - though cant recall the name as for now. try google uncle :)

Also if you wish to perform cross boundary optimization then you do nopt need to preserve the sub-modules - if you do not wish then you can preserve / dont_touch or I like the idea of libs

1) If I use the libs instead of sub-modules for Top-Level optimization, then who the final netlist should be assembled? Will the sub-modules still stay libs in the final Netlist?
2) Why to create libs for sub-modules and not just to read their netlists? What are the pros and cons?
3) Should I provide special commands/attributes for the cross boundary synthesis optimization?
4) What's difference between applying and not applying a flatten command on the hierarchical design during the synthesis? Will the difference be just in a netlist structure or also in the optimization results?
Thank you!

1. Yes
2. Cons - huge runtime, need to close / review timing again in this block, no need for formal verification again ; Pro - will be opposite of CON
3. If you using libs this is useless - since you cant go inside a hard logic and optimize
4. Difference will be in both cases Structure and optimization

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