Nov 26, 2009 #1 B bigdog Junior Member level 2 Joined Jul 18, 2005 Messages 24 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,452 Hello, I don't know how to stop my simulation, my testbench is described in VHDL and I use ncsim, is there any method to stop the simulation just like using $stop, $finish in Verilog? Regards,
Hello, I don't know how to stop my simulation, my testbench is described in VHDL and I use ncsim, is there any method to stop the simulation just like using $stop, $finish in Verilog? Regards,
Nov 26, 2009 #2 D devas Full Member level 2 Joined Jun 16, 2009 Messages 129 Helped 42 Reputation 84 Reaction score 11 Trophy points 1,298 Activity points 2,004 Hi, You can write at the end of your testbench: assert false report "end of simulation" severity failure; Devas
Hi, You can write at the end of your testbench: assert false report "end of simulation" severity failure; Devas
Nov 26, 2009 #3 B bigdog Junior Member level 2 Joined Jul 18, 2005 Messages 24 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,452 Hello Devas, Yes, the statement works! Thanks a lot! Regards,