How to speed-up the simulation of PLL

[yankuangtu]

It's lock time is about 100us
I use nanosim to simulate it,and i set up properly for the trade-pff between accuracy and speed - i think so
but the simulation is too slow,as pre-layout simulation,it takes 4 days to finish the simulation about 100us
Can someone guys share some experiences about speed-up the simulation of PLL?
thanks

 

[eng_Semi]

Behavioral models is the BEST solution

 

[playdc2002]

Try Hsim. for PLL simulation, usually, it is 2-4 times faster than hspice

 

[yankuangtu]

we now use nanosim,because we don't have the license for hsim.
I have to do the post-layout sim,we are evaluating the jitter of this PLL in out application

 

[rfsystem]

We get the about the same simulation times with HSIM. We use therefore HSIM only for functional verfification. If the package is included spectre is getting faster but still in the week range. Some difficult to understand coupling issues are only discovered after a complete spice simulation. Because of this I think there is is much help in using AHDL to improve understanding, verification and reuse but sometimes your modelling are lacking effects which are vital to your system and are only be visible in full spice.

Parallel spice is still in research and CPU stops speed upturn now. So no bright sight from the tools. The good thing about that is that it emphasize the more experienced desginers. Not everything could be simulated and mask are cost are n*100k$.

 

[sunking]

set initial state: such as the initail voltage on cap the initial current in inductor

 

[yankuangtu]

can some guys share me the info that:
how long take you to simulate the PLL,including:
1.which kind of simulator do you use
2.what is type pll do you simulate
3.how do you set up the simulator

thank u very much