How to specify input pattern in Cadence

[hertz]

Hi,

I am doing this 8-bit counter project. I need to calculate power consumption for this particular input pattern. I was wondering which symbol I can use to specify the voltage waveform pattern for my project?

What is the best way to calculate power in cadence?

Anybody knows? Please help!

Thanks,
Hertz

 

[Fom]

Yours project will be
1. pure analog?
2. pure digital?
3. mixed-signal?
What kind of waveform pattern do you need?
As I understand the only signal you need is clock. For this signal you can use simple pulse voltage source.
Of course if it is a programmable counter the pattern will be little more compicated.

 

[hertz]

It is pure digital. I need to make the increment control like:
1st cycle: reset
2nd cycle: INC
3rd cycle: INC
4th cycle: INC
5th cycle: INC
6th cycle: No INC
7th cycle: INC
8th cycle: No INC
and so on

 

[Fom]

For any pattern in digital design you can create another verilog (or VHDL) module that can generate this pattern. If you prefer graphical view you can create any symbol by yourself.
If you use standard cell library the library specification includes information about power. It should be specified in unit like "uW/MHz", because any digital logic consume power during transitions 0->1 or 1->0. So you can recalculate it to uW/Hz divide it by 2 and consider this coefficient as power for one event (0->1 or 1->0 transition). After that you can accumulate total event numbers multiply that by the coefficient and divide by time (in seconds). You can get power in uW.

 

[funzero]

Magma use VCD pattern file,