How to solve this clock violation??

[Nantha]

Hi all,
Please any one help me, how to clear this slack??? Is this false path??

______________________________________________
Path 1: VIOLATED Recovery Check with Pin U5_ClkResetGen/U_ClkGenGate/EnableD1_
reg/CLK
Endpoint: U5_ClkResetGen/U_ClkGenGate/EnableD1_reg/RB (^) checked with
leading edge of 'Clk696Rst'
Beginpoint: U5_ClkResetGen/SwRstNDelay2_reg/Q (^) triggered by
leading edge of 'Clk696Rst'
Other End Arrival Time 0.000
- Recovery 2695.200
+ Phase Shift 1196.000
= Required Time -1499.200
- Arrival Time 4095.400
= Slack Time -5594.600
Clock Rise Edge 0.000
+ Clock Network Latency (Ideal) 0.000
= Beginpoint Arrival Time 0.000
+-----------------------------------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required |
| | | | | Time | Time |
|------------------------------------------+--------------+---------------+----------+----------+-----------|
| U5_ClkResetGen/SwRstNDelay2_reg | CLK ^ | | | 0.000 | -5594.600 |
| U5_ClkResetGen/SwRstNDelay2_reg | CLK ^ -> Q ^ | SCVSDFFQRBXAA | 174.500 | 174.500 | -5420.100 |
| U5_ClkResetGen/p214748365A965 | B ^ -> Y ^ | SCVAND2XAA | 92.500 | 267.000 | -5327.600 |
| U5_ClkResetGen/U_Rst696ScMux | D0 ^ -> Y ^ | SCVMUX2XC1 | 3776.000 | 4043.000 | -1551.600 |
| U5_ClkResetGen/U_ClkGenGate/EnableD1_reg | RB ^ | SCVSDFFQRBXC1 | 52.400 | 4095.400 | -1499.200 |
+-----------------------------------------------------------------------------------------------------------+

 

[haykp]

Actually based on DC log, on-one can say whether the path is real or false. To be able to say whether the path is false or real you need to understand how the circuit works.
To be 100% sure that the path is false, you need to perform the SDF simulation of that block with timing violated.

You can send me the RTL and I will try to figure out whether the path is real or false.

---------- Post added at 15:57 ---------- Previous post was at 15:56 ----------

Actually based on DC log, on-one can say whether the path is real or false. To be able to say whether the path is false or real you need to understand how the circuit works.
To be 100% sure that the path is false, you need to perform the SDF simulation of that block with timing violated.

You can send me the RTL and I will try to figure out whether the path is real or false.

 

[Nantha]

Hi haykp,

I am working in Encounter. They declare every false path in Constraint file.. But my tool is not support for that false paths. That's y i am getting violation in same path what they were mention in sdc. How to solve this problem? please anyone help me..!

Rgds,
Nantha

 

[Nantha]

Is there any way to handle reset paths in encounter? I don't know how to handle this recovery and removal paths.. If i use timeDesign command, i'm getting lot of recovery and removal paths...
How to disable these reset paths???

 

[Kaisia]

setAnalysisMode -asyncChecks noAsync

 

[Nantha]

Hi kaisia,

Thanks a lot. I found that day itself.....