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How to simulate Post-P&R?

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blankcd

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I am beginner of losig design and simulation.

I want to do timing simulation using modelsim and Xilinx.
(using SDF file, verilog code not VHDL)

Someone explain me in detail, taking example.

have a nice day.
 

linuxluo

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Hi,
In modelsim you have to import your Xilinx .v library file first , and import your result .v file of your design , then import your sdf file attach to your top design module.
Now you can do your post simulation.
 

Al Farouk

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check the xilinx web site it has very good docummentation (App Note and tutorials) for FPGA Advantage flow and interation with xilinx tools

Al Farouk
 

ljkong

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maybe you can find all what you want in www.model.com.
there are many app notes .
good luck.
 

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