How to simulate Post-P&R?

[blankcd]

I am beginner of losig design and simulation.

I want to do timing simulation using modelsim and Xilinx.
(using SDF file, verilog code not VHDL)

Someone explain me in detail, taking example.

have a nice day.

 

[linuxluo]

Hi,
In modelsim you have to import your Xilinx .v library file first , and import your result .v file of your design , then import your sdf file attach to your top design module.
Now you can do your post simulation.

 

[blankcd]

I find!

Following Website

**broken link removed**

good document

 

[Al Farouk]

check the xilinx web site it has very good docummentation (App Note and tutorials) for FPGA Advantage flow and interation with xilinx tools

Al Farouk

 

[ljkong]

maybe you can find all what you want in www.model.com.
there are many app notes .
good luck.