Hugo17
Junior Member level 1
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Now I struggle to setup the control interface to access the ADC channels. Mainly following signals:
The interface description of the Read Master is:
The block diagram for the Read Master is:
Questions:
- How do I need to set the control signals to access the ADC channel x?
- Where can I find the base address for the ADC implemented in QSYS?
Maybe someone can give me an example how to simulate this interface in ModelSim.
Thanks in advance!
Now I struggle to setup the control interface to access the ADC channels. Mainly following signals:
- control_fixed_location
- control_read_base
- control_read_length
The interface description of the Read Master is:
The block diagram for the Read Master is:
Questions:
- How do I need to set the control signals to access the ADC channel x?
- Where can I find the base address for the ADC implemented in QSYS?
Maybe someone can give me an example how to simulate this interface in ModelSim.
Thanks in advance!