Thanks. Why does it make a setup violation? Is it setup violation possible that even though STA passed?Guess we see result of din setup timing violation.
the question is not whether it passed or not. the question is whether what you call STA is what hey call STA. your simulation environment might have wildly different assumptions than the STA checks performed by the backend team.Thanks. Why does it make a setup violation? Is it setup violation possible that even though STA passed?
What is setup time?
From recommands, I have searched Standard Cell Librat DATASHEET.the question is not whether it passed or not. the question is whether what you call STA is what hey call STA. your simulation environment might have wildly different assumptions than the STA checks performed by the backend team.
are you using an SDF file?From recommands, I have searched Standard Cell Librat DATASHEET.
Pin D has specific requirments.
setup (high ) 0.024997
setup (low) 0.034080
but when I check, sc9mcpp84_14lpu_base_lvt_c16.v there's are defined ARMSETUPTIMEandARMSETUPTIMEandAR_HOLD_TIME $setuphold(posedge CK &&& (ENABLE_NOT_D_AND_NOT_RAND_SI == 1'b1), negedge SE, ARMSETUPTIME,ARMSETUPTIME,ARM_HOLD_TIME, NOTIFIER, , ,dck,dSI);
From Here I'm confused that ARM_SETUP_TIME defined 1.0 and AR_HOLD_TIME is defined 0.5.
Do I need to modify Standard Cell Library verilog model defines as DATASHEET?
Yes, and use it $back_annotation(my_sdf,...,)are you using an SDF file?
I am still checking the same problem.Then you need to apply your engineering skills and understand if this a single path failing or several (all?) paths everywhere. This would indicate whether it is a timing problem or a simulation setup problem.
Also make sure the verilog code you are using for the std cells is appropriate for what you are doing. ARM, if I am not mistaken, has a lot of switches that you can turn on/off and the model will change accordingly. You have to make sure you are not using the unit model, where every gate takes 1 time unit to propagate a signal. This will never give you a timing-aware simulation.
I'm curious how you usually simulate in post-simulation when there is a timing violation between different clocks.Synchronizers and DCFIFOs should set false path(es) for the specific transfer(s). You should check if the reported violations are due to unwanted respectively unsafe clock crossings or due to improper constraints of intentional crossings.
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