Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to remove the delay from the output of DPLL(Urgent)

Status
Not open for further replies.

jawadysf

Newbie level 5
Joined
Nov 27, 2008
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,351
I am recovering the clock from the DPLL as manchester data as input to the DPLL.But when i implemented the DPLL on SPARTAN3 Board,output clock exhibits a delay from the input clock.
Can anyone suggest that how to remove this delay?
Its urgent

Thanks
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top