DZC
Full Member level 2
Hi, I want to buit a high speed Duty cycle corrector circuit.
The process is 0.18um CMOS.
The highest input and output clock frequency can be as high as 4GHz.
On wafer probe test will be chosen.
But I have no I idea how to built the I/O circuit.
Can I just get rid of the ESD circuit or which ESD circuit should I use?
How much parasitical capacitor of the PAD and probe should I consider?
Any otherthing should I take care of??
Thanks for all your kindly comment.
The process is 0.18um CMOS.
The highest input and output clock frequency can be as high as 4GHz.
On wafer probe test will be chosen.
But I have no I idea how to built the I/O circuit.
Can I just get rid of the ESD circuit or which ESD circuit should I use?
How much parasitical capacitor of the PAD and probe should I consider?
Any otherthing should I take care of??
Thanks for all your kindly comment.
