How to put the reg value in this color LCD controller code?

[aiko89]

Color LCD controller

module Lab1 (
Input DCLK_50, // 50 MHz
Input iKEY, // Pushbutton[3:0]
Input iSW, // Toggle Switch[17:0]
Output [7:0] LCM_DATA,LCM_HSYNC,LCM_VSYNC,LCM_GRST,LCM_SHDB,LCM_DCLK
); // LCM_DCLK is 50MHz, LCM_SHDB(logic 1)

reg [ ] H_Count;
reg [ ] V_Count;
reg [ ] Mod_Cnt;
reg [ ] Counter;
reg [ ] colour =8’d0;

always@(posedge DCLK_50MHz or negedge GRST)
// section a h_sync and h_ count generator, ref. 18.42 MHZ clock
//2. H_count count from 1 to 1171 then goes back to 1
//1. H_sync is always 1 expect when h_count =1 or reset.
//3. When reset(GRST), H_count is 1 and h_sync is 0

always@(posedge DCLK_50MHz or negedge GRST)
//section b LCM_VSYNC and V_count generator, ref. H_sync.
//1. V_Count increase by 1 every time H_count count for a cycle.
//2. V_Count count from 1 to 262 the goes back to 1
//3. V_sync is always 1 except when V_count=1 or reset
//4. When reset(GRST), V_Count is 1 and v_sync is 0


always@(posedge DCLK_50MHz or negedge GRST)
//Section C Display LCM_DATA in active area , and generate mod_cnt.
//1. Mod_cnt count from 0 to 2 when H_count and V_count within.
// range for valid data. Other times mod_cnt remains 3
//2. Assign LCM_DATA to different values according to mod_cnt
// to display different colour and use switch to control

endmodule



Starting of assign the reg value I already stuck and do not know how to put the reg value
And it come out got error because I put a wrong value
** Error: D:/Linda/assignment2/modelsim/lab1.v(10): Undefined variable: d0.
** Error: D:/Linda/assignment2/modelsim/lab1.v(10): near ";": syntax error, unexpected ';'

 

[lincoln2]

reg [7:0] colour =8’d0;

1. I think you are going to have to specify a bus width for all of your reg(s)
2. better expland from: forums.xilinx .c0m /t5/Synthesis/What-s-the-initial-value-for-a-register/td-p/55077

The initial value is always zero when not otherwise specified. This should be in the XST manual.

If not you might check the constraints guide. If your register has an asynchronous set or reset

term the initial value defaults to the same as the reset value. This is a simple way to set the

initial value without using the async reset by tying the module reset input to zero at a higher level. This

method also gives you a way to initialize your module during simulation even if you don't use

the asynchronous reset in hardware.



Of course it's better to be explicit in your source code so you don't create simulation

mis-matches. XST also allows initialization using an initial block in Verilog.



Regards,

Gabor

link

 

[Brownout]

reg [ ] colour =8’d0;


Should be : reg [ ] colour =8’b0; // "b" is for binary