ammmmlol
Newbie level 4
Hi,
I am trying to synthesize an adder like the one in Sparc T1-cpu.
The code contains two 16-bit adders like the following.
And the cell report looks like this.
DC treats DW adder as black box, don't touch and doesn't do any mapping. So I can't get any power or timing information.
I tried to remove one adder, and DC could actually synthesize one 16-bit adder. So I think there is no problem for DC mapping a 16-bit DW adder.
How do I tell DC to actually synthesize my module when I have multiple adders.
Thanks
I am trying to synthesize an adder like the one in Sparc T1-cpu.
The code contains two 16-bit adders like the following.
Code:
assign {cout16, adder_out[15:0]} = rs1_data[15:0] + rs2_data[15:0] + 1'b0;
assign {cout32, adder_out[31:16]} = rs1_data[31:16] + rs2_data[31:16] + cout16;
And the cell report looks like this.
PHP:
Cell Reference Library Area Attributes
--------------------------------------------------------------------------------
dp_cluster_0/add_1_root_add_39_2
DW01_add_17.blackbox.rpl 0.000000 b, d
dp_cluster_0/add_38 DW01_add_17.blackbox.rpl 0.000000 b, d
--------------------------------------------------------------------------------
Total 2 cells 0.000000
DC treats DW adder as black box, don't touch and doesn't do any mapping. So I can't get any power or timing information.
I tried to remove one adder, and DC could actually synthesize one 16-bit adder. So I think there is no problem for DC mapping a 16-bit DW adder.
How do I tell DC to actually synthesize my module when I have multiple adders.
Thanks