Cell Reference Library Area Attributes
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dp_cluster_0/add_1_root_add_39_2
DW01_add_17.blackbox.rpl 0.000000 b, d
dp_cluster_0/add_38 DW01_add_17.blackbox.rpl 0.000000 b, d
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Total 2 cells 0.000000
DC treats DW adder as black box, don't touch and doesn't do any mapping. So I can't get any power or timing information.
I tried to remove one adder, and DC could actually synthesize one 16-bit adder. So I think there is no problem for DC mapping a 16-bit DW adder.
How do I tell DC to actually synthesize my module when I have multiple adders.
Thanks
I am not sure about license checking. But if you can go through the run without any Error or critical Warning,
it seems license to be OK.
Is there any other Warning say that your combined design has DW component ?
As I remember, there is a warning with a reason for that DW to be existed after compiling by DC.