Virtex7 has I/O cell registers, why are you using flip-flops in the slices? The routing delay from the "nearest" slice isn't the same on every bank at every position, and the tools didn't always route them the same (though the tools may have improved over the 5-6 years, since I last had to deal with this issue).
If you are worried about clock skew between banks then put the output flip-flops in the I/O and put them on a separate clock network (use a PLL to output a 0 phase delay clock at the same frequency as the clock running the logic that feeds the outputs (the tools will handle the synchronous clock domain transfer between the logic and the I/O clock. The I/O clock delay difference between the banks should be as close as you will ever be able to manage (if you really needed that level of precision you should have kept them all in the same bank and or balanced the load of the clock network between the two banks, i.e. had the same number of outputs in both banks). If you have to, add more I/O registers to the design on unused pins if you can to help increase the I/O clock load on that bank.
The whole point of any of this is to get rid of variability so you can lock down the odelay values for design and make them constants, which you will not need to adjust on a per board basis (removing the need for any registers to control them).