skyworld_cy
Junior Member level 3
Hi,
I'm working with Xilinx Vertex 7. There is ADC bus input to the FPGA and DAC bus output from FPGA. Is there a good way to make these bus skew within a reasonable small range, for example, the difference of the routing length for each bit of the bus is less than 100ps? in that way, all data bit will arrive the end at the "same" time. Thanks.
I'm working with Xilinx Vertex 7. There is ADC bus input to the FPGA and DAC bus output from FPGA. Is there a good way to make these bus skew within a reasonable small range, for example, the difference of the routing length for each bit of the bus is less than 100ps? in that way, all data bit will arrive the end at the "same" time. Thanks.