If your asic vendor don't give you *.lib or *.db file (it is impossible
)
You can write a QTM module!
such as:
####Creating the Model and Setting Global Parameters####
1. Inform PrimeTime that a new model named “example” is being created.
create_qtm_model qtm_example
2. Specify the technology library to use with your design.
set_qtm_technology -library lib_new
3. Define a path type.
create_qtm_path_type path1 -lib_cell nand21 -fanout 2
4. Define a load type.
create_qtm_load_type load1 -lib_cell and22
5. Define the drive type.
create_qtm_drive_type drive1 -lib_cell buf1
create_qtm_drive_type drive2 -lib_cell buf2
6. Define a global setup time.
set_qtm_global_parameter -param setup -lib_cell DFF1 -clock CLK -pin D
7. Define a hold time.
set_qtm_global_parameter -param hold -value 0.0
8. Define a clock to the output delay time.
set_qtm_global_parameter -param clk_to_output -lib_cell DFF1 -clock CLK -pin Q
####Specifying Model Information####
1. Create a clock port.
create_qtm_port {CLK} -type clock
2. Create the input ports.
create_qtm_port {A B} -type input
3. Create the output ports.
create_qtm_port {X Y} -type output
4. Set the load1 load type on the A and B ports.
set_qtm_port_load {A B} -type load1 -factor 2
5. Set a load of three capacitance units on CLK.
set_qtm_port_load {CLK} -value 3
6. Set a drive on the output ports.
set_qtm_port_drive X -type drive1
set_qtm_port_drive Y -type drive2
7. Define the setup and hold arcs.
create_qtm_constraint_arc -setup -edge rise \
-name SetupA -from CLK -to A -path_type \
path1 -path_factor 2
create_qtm_constraint_arc -hold -edge rise \
-name HoldA -from CLK -to A -path_type \
path 1 -path_factor 2
8. Create the delay arcs.
create_qtm_delay_arc -name BtoY -from B -to Y -path_type path1 -path_factor 3
create_qtm_delay_arc -name CLKtoX -from CLK -to X -path_type path1 -path_factor 2