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How to instance a Hardmacro/memory in DesignComiler

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aramis

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Hi,
I have a question when instance a Memory(from artisan) in my design.
Is my flow correct??

1. write a empty model , ex: module A16x16();
2. in my design, i instace the empty module

3. In DC, read my all design include the empty moule,
set the link_library path to the actual memory A16x16.db

4. command > link, the DC link my all desgin

5. command > set_dont_touch "the A16x16 module"

6. compile and report timing


Am i correct ?? or i don't need to write a empty module??

if i don't give link and set_dont_touch command, just compile it, can i get a correct timing and correct sdf file??
because i have refernce to someone else's dc script, they don't do this, they just read and compile. so i'm so confused!!

Can someone help me!!


Thanks

aramis
 

cnz

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If you only study asic design flow,you can write a QTM module by PT!
if not,your asic vendor must give *.lib or .db library to you !
 

farmerwang

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If you use Artisan, they will provide memory compiler, which you can used to generated Memory Macro cells in all formats. For DC, first translate the generated .lib file to .db format, then put them in the link_library list.
 

aramis

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farmerwang said:
If you use Artisan, they will provide memory compiler, which you can used to generated Memory Macro cells in all formats. For DC, first translate the generated .lib file to .db format, then put them in the link_library list.
Thank you very much, my question is that should i need to write a seperate empty module and instance it , or just instance this module??

Ex:

module RAM16x16(...)
endmodule

RAM16x16 Ra1(....)


or just
RAM16x16 Ra1(....)
 

cnz

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If your asic vendor don't give you *.lib or *.db file (it is impossible :) )

You can write a QTM module!
such as:
####Creating the Model and Setting Global Parameters####
1. Inform PrimeTime that a new model named “example” is being created.
create_qtm_model qtm_example

2. Specify the technology library to use with your design.
set_qtm_technology -library lib_new

3. Define a path type.
create_qtm_path_type path1 -lib_cell nand21 -fanout 2

4. Define a load type.
create_qtm_load_type load1 -lib_cell and22

5. Define the drive type.
create_qtm_drive_type drive1 -lib_cell buf1
create_qtm_drive_type drive2 -lib_cell buf2

6. Define a global setup time.
set_qtm_global_parameter -param setup -lib_cell DFF1 -clock CLK -pin D

7. Define a hold time.
set_qtm_global_parameter -param hold -value 0.0

8. Define a clock to the output delay time.
set_qtm_global_parameter -param clk_to_output -lib_cell DFF1 -clock CLK -pin Q



####Specifying Model Information####
1. Create a clock port.
create_qtm_port {CLK} -type clock

2. Create the input ports.
create_qtm_port {A B} -type input

3. Create the output ports.
create_qtm_port {X Y} -type output


4. Set the load1 load type on the A and B ports.
set_qtm_port_load {A B} -type load1 -factor 2

5. Set a load of three capacitance units on CLK.
set_qtm_port_load {CLK} -value 3

6. Set a drive on the output ports.
set_qtm_port_drive X -type drive1
set_qtm_port_drive Y -type drive2

7. Define the setup and hold arcs.
create_qtm_constraint_arc -setup -edge rise \
-name SetupA -from CLK -to A -path_type \
path1 -path_factor 2
create_qtm_constraint_arc -hold -edge rise \
-name HoldA -from CLK -to A -path_type \
path 1 -path_factor 2

8. Create the delay arcs.
create_qtm_delay_arc -name BtoY -from B -to Y -path_type path1 -path_factor 3
create_qtm_delay_arc -name CLKtoX -from CLK -to X -path_type path1 -path_factor 2
 

cnz

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You need not write the empty module .
After PT run the script,PT can generate the *.db and *_lib.db file!

in DC,you just add the *_lib.db to the link_library variable and
read *.db into memory.

You can refer to SOLD about it !
 

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