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If your load and FS current are fixed and If You need to design DAC operating with higher sampling frequency without dynamic behaviour deterioration (the same SFDR, SNHR, etc) You need to increase output impedance of DAC for this frequency (SFDR ~ Zout/Rload) and proper design of digital part.
Look for the Van den Bosch, Borremnas and Steyart papers about high speed nyquist DACs.
It's more likely that settling time is what's limiting
you, and with fixed load attributes the only thing
that will let you run faster sample rate is lower
accuracy expectations. Presuming you are accuracy
limited now. And what -is- limiting you now?
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