thx
efundas said:
The start point is the clock itself(xt_aclk) so it is a part of CTS and in the logic synthesis this should be put as a false path.
but ,how do the following path add constrain?
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Startpoint: SUBTOP/U_REG/U2/Data_Out_reg
(falling edge-triggered flip-flop clocked by TX_ZT_ECLK)
Endpoint: RTX_ZT_EDOUT
(output port clocked by TX_ZT_ECLK)
Path Group: TX_ZT_ECLK
Path Type: max
Point Incr Path
------------------------------------------------------------------------------
clock TX_ZT_ECLK (fall edge) 640.00 640.00
clock network delay (ideal) 0.00 640.00
SUBTOP/U_REG/U2/Data_Out_reg/CKN (DFFNRX1) 0.00 640.00 f
SUBTOP/U_REG/U2/Data_Out_reg/Q (DFFNRX1) 1.14 641.14 r
SUBTOP/U_REG/U2/Data_Out (EEPROM) 0.00 641.14 r
SUBTOP/U_REG/Eprom_Dout (REGMODULE) 0.00 641.14 r
SUBTOP/EEPROM_DATA_OUT_OUTREG (ZX2701_SUBTOP) 0.00 641.14 r
U199/PAD (WC3B82UA) 2.08 643.22 r
RTX_ZT_EDOUT (inout) 0.00 643.22 r
data arrival time 643.22
clock TX_ZT_ECLK (rise edge) 1280.00 1280.00
clock network delay (ideal) 0.00 1280.00
output external delay -1254.00 26.00
data required time 26.00
------------------------------------------------------------------------------
data required time 26.00
data arrival time -643.22
------------------------------------------------------------------------------
slack (VIOLATED) -617.22
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