Re: STA report
Hi ,
Just summrising possibilities
1) Fanout - If wire is driving somany pins , for this you can do high fanout synth in DC and carryout your timing analyis , but better create a ideal net so that you don't see these issues as these issues are fixed in CTS stage.
2) Bad Driver - look at delay table for the cell , you can avoid this by chaning cell
3) Tranistion for neg edge - some cells have diffrent delay for neg and pos , use appropriate cells for the same .
Thanks & Regards
yln