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How to improve large transition time for a gate element in STA?

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hover

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First I would like to thank those ones who help me on the former topic STA problem. Now I have a new problem that from the timing report I found that there is a large transition time for a gate element in my gate level netlist. Because this is a pre-layout STA. So can anybody tell me that what kind of factors caused this problem and what kind of measures can be taken to solve this problem.
 

Re: STA report

check the driver of gate.
 

Re: STA report

Hi Hover,
The problem is with the Load at that cell which is causing this timing problem. You can use High Fanout synthesis for that cell element. It will solve this problem.
Also I'm considering that its a Pre-Cts netlist. If it is so then that may be CTS can solve your timing problem.

Thanks
 

Re: STA report

Hi ,

Just summrising possibilities


1) Fanout - If wire is driving somany pins , for this you can do high fanout synth in DC and carryout your timing analyis , but better create a ideal net so that you don't see these issues as these issues are fixed in CTS stage.
2) Bad Driver - look at delay table for the cell , you can avoid this by chaning cell
3) Tranistion for neg edge - some cells have diffrent delay for neg and pos , use appropriate cells for the same .


Thanks & Regards
yln
 

Re: STA report

It can be due to high -fanout. (high load). Check if the cell is driving to many cells. It will be good If you can post timing report.
 

Re: [STA] Transition Time

It can be due to high -fanout. (high load). Check if the cell is driving to many cells. It will be good If you can post timing report.

How does the tools calculate Transition Delay over the net/pin?

I know that propagation delay is calculated using NLDM tables, overall delays using WLM, but what about Transition Time calculations?
 

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