How to implement Divider in Xilinx FPGA (NOT CLOCK DIVIDER)

ukyo · Mar 25, 2004

xilinx divider

Thanks in advanced!

I need divider for my thesis job!
Details is Fixed point,
Dividend = 32 bit
Divisor = 16 bit
Quotient <= 30 bit
Reminder = 16bit

Frequency minimum = 70 MHZ
RTL code sample
Xilinx FPGA VII 6000 -4
Thanks again
[/img]

brmadhukar · Mar 27, 2004

divider fpga

Hi there are many methods to do this. You can refer a cody and waites books for this. There are many IEEE papers on this. search google for "division algorithms fixed point"
BRM

vomit · Mar 27, 2004

xilinx clock divider

ukyo said:
Thanks in advanced!
Frequency minimum = 70 MHZ
RTL code sample
Xilinx FPGA VII 6000 -4
Thanks again
[/img]

Check out
* Xilinx Core Generator
* CORDIC algorithms on Google
e.g. https://www.convict.lu/Jeunes/Math/Fast_operations2.htm

How to implement Divider in Xilinx FPGA (NOT CLOCK DIVIDER)

ukyo

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brmadhukar

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vomit

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How to implement Divider in Xilinx FPGA (NOT CLOCK DIVIDER)

ukyo

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