How to implement Divider in Xilinx FPGA (NOT CLOCK DIVIDER)

[ukyo]

xilinx divider

Thanks in advanced!

I need divider for my thesis job!
Details is Fixed point,
Dividend = 32 bit
Divisor = 16 bit
Quotient <= 30 bit
Reminder = 16bit

Frequency minimum = 70 MHZ
RTL code sample
Xilinx FPGA VII 6000 -4
Thanks again
[/img]

 

[brmadhukar]

divider fpga

Hi there are many methods to do this. You can refer a cody and waites books for this. There are many IEEE papers on this. search google for "division algorithms fixed point"
BRM

 

[vomit]

xilinx clock divider

Thanks in advanced!
Frequency minimum = 70 MHZ
RTL code sample
Xilinx FPGA VII 6000 -4
Thanks again
[/img]

Check out
* Xilinx Core Generator
* CORDIC algorithms on Google
e.g. https://www.convict.lu/Jeunes/Math/Fast_operations2.htm