how to identify timing loops in design compiler

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mepriyasingh

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i want to know that if suppose i found that there are 5 timing loops in my design by loop report. then how can trace the input and output of timing loos.
 

Try "check_timing -include {loop}" will help to report all cell/pin in the loop. Mostly loop issue can be broken by set_disable_timing command if you know an timing arc is constant or does not exist in your current mode of operation.
 
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