Hi I need to pass my output through a D FF.
i.e. IF I set clk enable= 1; o/p should be equal to input but
when clk enable =0 output should be 0 .
For this am hard coding set= 0 and reset = 0. But my input pattern is changing with clock. So what should I do to get the same input pattern??!!!
bad code. This IS NOT a flip-flop; I don't know what it is.
1) your rising_edge statement should be ELSIF, not IF
2) I think it's just my personal preference inside clocked processes, but you will definitely avoid problems if you have an ELSE to go along with your IFs. (You DEFINITELY need the else for non-clocked processes)
3) You made this too complex. You could have just had:
Code VHDL - [expand]
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if rst='1' then
q<='0';elsif rising_edge(clk)then
q<=data;endif;
Thanku Barry. I took your suggestion and changed the code as below . But am not able to get the same output as input. this is happening because the clock might not to be high when the input changes. So there is a loss in the data. But How can I get the input pattern using a clock.
Changed code:
Code:
process(d, clk, ce, reset)
begin
if reset='1' then
q<='0';
elsif rising_edge(clk) and ce= '1' then
q<=d;
elsif ce = '0' then
q <= '0';
end if;
end process;