How to get the same input pattern?

[shiny1]

Hi I need to pass my output through a D FF.
i.e. IF I set clk enable= 1; o/p should be equal to input but
when clk enable =0 output should be 0 .
For this am hard coding set= 0 and reset = 0. But my input pattern is changing with clock. So what should I do to get the same input pattern??!!!

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
entity DFF is
 
port 
(
clk : in std_logic;
clk_ena : in std_logic;
data : in std_logic;
reset : in std_logic; 
q : out std_logic 
);
 
end entity;
architecture....
signal internal_state : std_logic;
 
begin
 
process(data, clk, clk_ena, reset)
begin
if(reset = '0') then
if rising_edge(clk) then
if(clk_ena = '1') then
internal_state <= data; --latch input 
end if;
q <= internal_state;
end if;
else
internal_state <= '0';
end if;
end process;

---

 

[barry]

Re: whats wrong with this

bad code. This IS NOT a flip-flop; I don't know what it is.

1) your rising_edge statement should be ELSIF, not IF
2) I think it's just my personal preference inside clocked processes, but you will definitely avoid problems if you have an ELSE to go along with your IFs. (You DEFINITELY need the else for non-clocked processes)
3) You made this too complex. You could have just had:

---

Code VHDL - [expand]
1
2
3
4
5
if rst='1' then 
          q<='0';
elsif rising_edge(clk) then
          q<=data;
end if;

---

 

[shiny1]

Re: whats wrong with this -DFF

Thanku Barry. I took your suggestion and changed the code as below . But am not able to get the same output as input. this is happening because the clock might not to be high when the input changes. So there is a loss in the data. But How can I get the input pattern using a clock.

Changed code:

process(d, clk, ce, reset)
begin
if reset='1' then 
          q<='0';
elsif rising_edge(clk)  and ce= '1' then
          q<=d;
elsif ce = '0' then
 q <= '0';			 
end if;
end process;

 

[barry]

Re: whats wrong with this

Still not good form. And STILL not a D-FF(as I showed).

You can't have two elsifs like that.

Try this:

begin
if reset='1' then
q<='0';
elsif rising_edge(clk) then
if ce= '1' then
q<=d;
else
q <= '0';
end if;
end if;
end process;